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9.3.12 DMAC Access from CPU .................................................................................... 178
9.4
Examples of Use................................................................................................................ 178
9.4.1
Example of DMA Transfer between On-Chip SCI and External Memory.......... 178
9.4.2
Example of DMA Transfer between External RAM and External Device
with DACK .......................................................................................................... 179
9.5
Cautions on Use................................................................................................................. 180
Section 10 Multifunction Timer Pulse Unit (MTU).................................................. 181
10.1
Overview............................................................................................................................ 181
10.1.1 Features ................................................................................................................ 181
10.1.2 Block Diagram...................................................................................................... 185
10.1.3 Pin Configuration ................................................................................................. 186
10.1.4 Register Configuration ......................................................................................... 187
10.2
MTU Register Descriptions ............................................................................................... 188
10.2.1 Timer Control Register (TCR) ............................................................................. 188
10.2.2 Timer Mode Register (TMDR) ............................................................................ 192
10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 194
10.2.4 Timer Interrupt Enable Register (TIER) .............................................................. 202
10.2.5 Timer Status Register (TSR) ................................................................................ 204
10.2.6 Timer Counters (TCNT)....................................................................................... 207
10.2.7 Timer General Register (TGR) ............................................................................ 208
10.2.8 Timer Start Register (TSTR)................................................................................ 208
10.2.9 Timer Synchro Register (TSYR).......................................................................... 209
10.3
Bus Master Interface.......................................................................................................... 210
10.3.1 16-Bit Registers.................................................................................................... 210
10.3.2 8-Bit Registers...................................................................................................... 211
10.4
Operation ........................................................................................................................... 212
10.4.1 Overview .............................................................................................................. 212
10.4.2 Basic Functions .................................................................................................... 212
10.4.3 Synchronous Operation ........................................................................................ 218
10.4.4 Buffer Operation .................................................................................................. 221
10.4.5 Cascade Connection Mode ................................................................................... 224
10.4.6 PWM Mode .......................................................................................................... 226
10.4.7 Phase Counting Mode .......................................................................................... 230
10.5
Interrupts............................................................................................................................ 236
10.5.1 Interrupt Sources and Priority Ranking................................................................ 236
10.5.2 DMAC Activation ................................................................................................ 237
10.5.3 A/D Converter Activation .................................................................................... 237
10.6
Operation Timing .............................................................................................................. 238
10.6.1 Input/Output Timing ............................................................................................ 238
10.6.2 Interrupt Signal Timing ........................................................................................ 242
10.7
Notes and Precautions........................................................................................................ 246
10.7.1 Input Clock Limitations........................................................................................ 246