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8.4
DRAM Access ................................................................................................................... 119
8.4.1
DRAM Direct Connection.................................................................................... 119
8.4.2
Basic Timing ........................................................................................................ 120
8.4.3
Wait State Control ................................................................................................ 121
8.4.4
Burst Operation .................................................................................................... 125
8.4.5
Refresh Timing ..................................................................................................... 127
8.5
Address/Data Multiplex I/O Space Access........................................................................ 128
8.5.1
Basic Timing ........................................................................................................ 128
8.5.2
Wait State Control ................................................................................................ 130
8.5.3
CS Assort Extension............................................................................................. 131
8.6
Waits between Access Cycles ........................................................................................... 132
8.6.1
Prevention of Data Bus Conflicts ......................................................................... 132
8.6.2
Simplification of Bus Cycle Start Detection ........................................................ 133
8.7
Bus Arbitration .................................................................................................................. 134
8.8
Memory Connection Examples ......................................................................................... 134
8.9
On-chip Peripheral I/O Register Access............................................................................ 136
8.10
CPU Operation when Program is in External Memory ..................................................... 137
Section 9
Direct Memory Access Controller (DMAC).......................................... 139
9.1
Overview............................................................................................................................ 139
9.1.1
Features ................................................................................................................ 139
9.1.2
Block Diagram...................................................................................................... 140
9.1.3
Pin Configuration ................................................................................................. 141
9.1.4
Register Configuration ......................................................................................... 142
9.2
Register Descriptions......................................................................................................... 143
9.2.1
DMA Source Address Registers 0, 1 (SAR0, SAR1) .......................................... 143
9.2.2
DMA Destination Address Registers 0, 1 (DAR0, DAR1).................................. 143
9.2.3
DMA Transfer Count Registers 0, 1 (DMATCR0, DMATCR1) ........................ 144
9.2.4
DMA Channel Control Registers 0, 1 (CHCR0, CHCR1) ................................... 145
9.2.5
DMAC Operation Register (DMAOR) ................................................................ 149
9.3
Operation ........................................................................................................................... 151
9.3.1
DMA Transfer Flow ............................................................................................. 151
9.3.2
DMA Transfer Requests....................................................................................... 153
9.3.3
Channel Priority.................................................................................................... 155
9.3.4
DMA Transfer Types ........................................................................................... 155
9.3.5
Address Modes ..................................................................................................... 156
9.3.6
Dual Address Mode.............................................................................................. 157
9.3.7
Bus Modes............................................................................................................ 160
9.3.8
Relationship between Request Modes and Bus Modes by DMA
Transfer Category ................................................................................................. 161
9.3.9
Bus Mode and Channel Priority Order ................................................................. 162
9.3.10 Number of Bus Cycle States and
DREQ Pin Sample Timing.............................. 162
9.3.11 DMA Transfer Ending Conditions ....................................................................... 177