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Section 9 Direct Memory Access Controller (DMAC)
9.1
Overview
The SH7014 includes an on-chip two-channel direct memory access controller (DMAC). The
DMAC can be used in place of the CPU to perform high-speed data transfers among external
devices equipped with DACK (transfer request acknowledge signal), external memories, memory-
mapped external devices, and on-chip peripheral modules (except for the DMAC and BSC). Using
the DMAC reduces the burden on the CPU and increases operating efficiency of the LSI as a
whole.
9.1.1
Features
The DMAC has the following features:
Two channels
Four Gbytes of address space in the architecture
Byte, word, or longword selectable data transfer unit
64 k (65,536) transfers
Single or dual address mode.
Single address mode: Either the transfer source or transfer destination (peripheral device) is
accessed by a DACK signal while the other is accessed by address. One transfer unit of
data is transferred in each bus cycle.
Dual address mode: Both the transfer source and transfer destination are accessed by
address. Values set in a DMAC internal register indicate the accessed address for both the
transfer source and transfer destination. Two bus cycles are required for one data transfer.
Channel function: Dual address mode and single address mode external requests can be
accepted.
Transfer requests: There are three DMAC transfer activation requests, as indicated below.
External request: From two DREQ pins. DREQ can be detected either by falling edge or by
low level.
Requests from on-chip peripheral modules: Transfer requests from on-chip modules such as
SCI or A/D. These can be received by all channels.
Auto-request: The transfer request is generated automatically within the DMAC.
Selectable bus modes: Cycle-steal mode or burst mode
The DMAC priority order is fixed at 0 > 1.