![](http://datasheet.mmic.net.cn/120000/SH7017F_datasheet_3575229/SH7017F_13.png)
vii
12.1.2 Block Diagram...................................................................................................... 290
12.1.3 Pin Configuration ................................................................................................. 291
12.1.4 Register Configuration ......................................................................................... 291
12.2
Register Descriptions......................................................................................................... 292
12.2.1 Receive Shift Register (RSR) ............................................................................... 292
12.2.2 Receive Data Register (RDR) .............................................................................. 292
12.2.3 Transmit Shift Register (TSR).............................................................................. 292
12.2.4 Transmit Data Register (TDR) ............................................................................ 293
12.2.5 Serial Mode Register (SMR)................................................................................ 293
12.2.6 Serial Control Register (SCR).............................................................................. 296
12.2.7 Serial Status Register (SSR) ................................................................................. 299
12.2.8 Bit Rate Register (BRR) ....................................................................................... 303
12.3
Operation ........................................................................................................................... 318
12.3.1 Overview .............................................................................................................. 318
12.3.2 Operation in Asynchronous Mode........................................................................ 320
12.3.3 Multiprocessor Communication ........................................................................... 330
12.3.4 Clock Synchronous Operation.............................................................................. 338
12.4
SCI Interrupt Sources and the DMAC............................................................................... 349
12.5
Notes on Use...................................................................................................................... 350
12.5.1 TDR Write and TDRE Flags ................................................................................ 350
12.5.2 Simultaneous Multiple Receive Errors ................................................................ 350
12.5.3 Break Detection and Processing ........................................................................... 351
12.5.4 Sending a Break Signal ........................................................................................ 351
12.5.5 Receive Error Flags and Transmitter Operation (Clock Synchronous
Mode Only) .......................................................................................................... 351
12.5.6 Receive Data Sampling Timing and Receive Margin in the
Asynchronous Mode ............................................................................................ 351
12.5.7 Constraints on DMAC Use .................................................................................. 353
12.5.8 Cautions for Clock Synchronous External Clock Mode ...................................... 353
12.5.9 Caution for Clock Synchronous Internal Clock Mode ......................................... 353
Section 13 High Speed A/D Converter –SH7014–.................................................... 355
13.1
Overview............................................................................................................................ 355
13.1.1 Features ................................................................................................................ 355
13.1.2 Block Diagram...................................................................................................... 356
13.1.3 Pin Configuration ................................................................................................. 356
13.1.4 Register Configuration ......................................................................................... 357
13.2
Register Descriptions......................................................................................................... 358
13.2.1 A/D Data Registers A–H (ADDRA–ADDRH).................................................... 358
13.2.2 A/D Control/Status Register (ADCSR)................................................................ 359
13.2.3 A/D Control Register (ADCR) ............................................................................. 362
13.3
Bus Master Interface.......................................................................................................... 363
13.4
Operation ........................................................................................................................... 366