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参数资料
型号： SI3011-F-FS
厂商： Silicon Laboratories Inc
文件页数： 47/128页
文件大小： 0K
描述： IC VOICE DAA GCI/PCM/SPI 16SOIC
标准包装： 48
系列： ISOcap™
电源电压： 3 V ~ 3.6 V
安装类型： 表面贴装
封装/外壳： 16-SOIC（0.154"，3.90mm 宽）
供应商设备封装： 16-SOIC N
包装： 管件
Si3050 + Si3011/18/19
Rev. 1.5
25
5.2. Power Supplies
The Si3050 operates from a 3.3 V power supply. The
Si3050 input pins require 3.3 V CMOS signal levels. If
support of 5 V signal levels is necessary, a level shifter
is required. The Si3011/18/19 derives its power from
two sources: the Si3050 and the telephone line. The
Si3050 supplies power over the patented isolation
capacitor link between the two devices, allowing the
line-side device to communicate with the Si3050 while
on-hook, and perform other on-hook functions such as
line voltage monitoring. When off-hook, the line-side
device also derives power from the line current supplied
from the telephone line. This feature is exclusive to
DAAs
from
Silicon
Labs
and
allows
the
most
cost-effective implementation for a DAA while still
maintaining robust performance over all line conditions.
5.3. Initialization
Each time the Si3050 is powered up, assert the RESET
pin. When the RESET pin is deasserted, the registers
have default values to guarantee the line-side device
(Si3011/18/19) is powered down without the possibility
of
loading
the
line
(i.e.,
off-hook).
An
example
initialization procedure follows:
1. Power up and de-assert RESET.
2. Wait until the PLL is locked. This time is less than
1 ms from the application of PCLK.
3. Enable PCM (Register 33) or GCI (Register 42)
mode.
4. Set the desired line interface parameters (i.e.,
DCV[1:0], MINI[1:0], ILIM, DCR, ACIM[3:0], OHS,
RT, RZ, TGA2, and TXG2[3:0]) shown in Table 13 on
page 22.
5. Set the FULL (or FULL2) + IIRE bits as required.
6. Write a 0x00 into Register 6 to power up the
line-side device (Si3011/18/19).
When this procedure is complete, the Si3011/18/19 is
ready for ring detection and off-hook operation.
5.4. Isolation Barrier
The Si3050 achieves an isolation barrier through
low-cost, high-voltage capacitors in conjunction with
Silicon
Laboratories’
patented
signal
processing
techniques.
Differential
capacitive
communication
eliminates
signal
degradation
from
capacitor
mismatches, common mode interference, or noise
coupling. As shown in the "2. Typical Application
Schematic" on page 17, the C1, C2, C8, and C9
capacitors isolate the Si3050 (system-side) from the
Si3011/18/19 (line-side). Transmit, receive, control, ring
detect, and caller ID data are passed across this barrier.
The communications link is disabled by default. To
enable it, the PDL bit (Register 6, bit 4) must be
cleared. No communication between the Si3050 and
Si3018/19 can occur until this bit is cleared. Allow the
PLL to lock to the PCLK and FSYNC input signals
before clearing the PDL bit.
5.5. Power Management
The Si3050 supports four basic power management
operation modes. The modes are normal operation,
reset operation, sleep mode, and full powerdown mode.
The power management modes are controlled by the
PDN and PDL bits (Register 6).
On powerup, or following a reset, the Si3050 is in reset
operation. The PDL bit is set, and the PDN bit is
cleared. The Si3050 is operational, except for the
communications link. No communication between the
Si3050 and line-side device (Si3011/18/19) can occur
during reset operation. Bits associated with the line-side
device are invalid in this mode.
In typical applications, the DAA will predominantly be
operated in normal mode. In normal mode, the PDL and
PDN bits are cleared. The DAA is operational and the
communications link passes information between the
Si3050 and the Si3011/18/19.
The Si3050 supports a low-power sleep mode that
supports ring validation and wake-up-on-ring features.
To enable the sleep mode, the PDN bit must be set.
When the Si3050 is in sleep mode, the PCLK signal
must remain active. In low-power sleep mode, the
Si3050 is non-functional except for the communications
link and the RGDT signal. To take the Si3050 out of
sleep mode, pulse the reset pin (RESET) low.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure the PDL bit (Register 6, bit 4) is cleared.
2. Set the PDN bit (Register 6, bit 3).
3. The device is now in sleep mode. PCLK must remain
active.
4. To exit sleep mode, reset the Si3050 by pulsing the
RESET pin.
5. Program registers to desired settings.
The Si3050 also supports an additional Powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the Si3050 is
non-functional. The RGDT pin does not function and the
Si3050 will not detect a ring. Normal operation can be
restored using the same process for taking the Si3050
out of sleep mode.
相关PDF资料
PDF描述
SI3012-KS IC LINE-SIDE DAA 16SOIC
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相关代理商/技术参数
参数描述
SI3011-F-FSR 功能描述:电信线路管理 IC Si3050 FCC/TBR21 Voice DAA Line-Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray
Si3011-F-FT 功能描述:电信语音调制 IC Si3050 FCC/TBR21 Voice DAA Line-Side RoHS:否 制造商:Epson Electronics America 产品: 应用:Voice Guidance product 封装 / 箱体:PQFP-52 电源电压-最大:3.6 V, 5.5 V 最大工作温度: 最小工作温度: 封装:
SI3011-F-FTR 制造商:Silicon Laboratories Inc 功能描述:SI3050 FCC/TBR21 VOICE DAA LINE-SIDE - LEAD-FREE - Tape and Reel
SI3011-F-GM 制造商:SILABS 制造商全称:SILABS 功能描述:PROGRAMMABLE VOICE DAA SOLUTIONS
SI3011-F-GS 制造商:SILABS 制造商全称:SILABS 功能描述:PROGRAMMABLE VOICE DAA SOLUTIONS
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