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| 型号： | SI3011-F-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 48/128页 |
| 文件大小： | 0K |
| 描述： | IC VOICE DAA GCI/PCM/SPI 16SOIC |
| 标准包装： | 48 |
| 系列： | ISOcap™ |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
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Si3050 + Si3011/18/19
26
Rev. 1.5
5.6. Calibration
The Si3050 initiates two auto-calibrations by default
when the device goes off-hook or experiences a loss of
line power. A 17 ms resistor calibration is performed to
allow circuitry internal to the DAA to adjust to the exact
line conditions present at the time of going off-hook.
This resistor calibration can be disabled by setting the
RCALD
bit
(Register 25, bit 5).
A
256 ms
ADC
calibration is also performed to remove offsets that
might be present in the on-chip A/D converter, which
could affect the A/D dynamic range.
The ADC
auto-calibration is initiated after the DAA dc termination
stabilizes and the resistor calibration completes. Due to
the large variation in line conditions and line card
behavior presented to the DAA, it might be beneficial to
use manual ADC calibration instead of auto-calibration.
Manual ADC calibration should be executed as close as
possible to 256 ms before valid transmit/receive data is
expected.
The following steps should be taken to implement
manual ADC calibration:
1. The CALD bit (auto-calibration disable—Register 17)
must be set to 1.
2. The MCAL bit (manual calibration) must be toggled
to one and then 0 to begin and complete the
calibration.
3. The calibration is completed in 256 ms.
5.7. In-Circuit Testing
The Si3050’s advanced design provides the designer
with
an
increased
ability
to
determine
system
functionality during production line tests and support for
end-user
diagnostics.
Six
loopback
modes
allow
increased coverage of system components. For four of
the test modes, a line-side power source is needed.
While a standard phone line can be used, the test circuit
in Figure 1 on page 6 is adequate. In addition, an
off-hook sequence must be performed to connect the
power source to the line-side device.
For the start-up loopback test mode, no line-side power
is necessary, and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a powerdown mode, and the system-side is in
a digital loopback mode. In this mode, data received on
DRX
passes
through
the
internal
filters
and
is
transmitted on DTX. This path introduces approximately
0.9 dB of attenuation on the DRX signal received. The
group delay of both transmit and receive filters exists
between DRX and DTX. Clearing the PDL bit disables
this mode, and the DTX data switches to the receive
data from the line side. When the PDL bit is cleared, the
FDT bit (Register 12, bit 6) becomes active to indicate
that successful communication between the line side
and
system
side
is
established.
This
provides
verification that the communications link is operational.
The digital data loop-back mode offers a way to input
data on the DRX pin and have the identical data output
on the DTX pin through bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
enables this mode, which provides an easy way to verify
communication between the host processor/DSP and
the DAA. No line-side power or off-hook sequence is
required for this mode.
The remaining test modes require an off-hook sequence
to operate. The following sequence lists the off-hook
requirements:
1. Powerup or reset.
2. Allow the internal PLL to lock on PCLK and FSYNC.
3. Enable line-side by clearing PDL bit.
4. Issue an off-hook command.
5. Delay 402.75 ms for calibration to occur.
6. Set desired test mode.
The communications link digital loopback mode allows
the host processor to provide a digital input test pattern
on DRX and receive that digital test pattern back on
DTX. To enable this mode, set the IDL bit (Register 1,
bit 1). The communications link is tested in this mode.
The digital stream is delivered across the isolation
capacitors, C1 and C2, of the "2. Typical Application
Schematic" on page 17, to the line-side device and
returned across the same path. In this digital loopback
mode, the 0.9 dB attenuation and filter group delays
also exist.
The PCM analog loopback mode extends the signal
path of the analog loopback mode. In this mode, an
analog signal is driven from the line into the line-side
device. This analog signal is converted to digital data
and then passed across the communications link to the
system-side device. The data passes through the
receive filter, through the transmit filter, and is then
passed across the communications link and sent back
out onto the line as an analog signal. Set the PCML bit
(Register 33, bit 7) to enable this mode.
With the final testing mode, internal analog loopback,
the system can test the operation of the transmit and
receive paths on the line-side device and the external
components in the "2. Typical Application Schematic"
on page 17. The host provides a digital test waveform
on DRX. Data passes across the isolation barrier, is
transmitted to and received from the line, passes back
across the isolation barrier, and is presented to the host
on DTX. Clear the HBE bit (Register 2, bit 1) to enable
this mode.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3011-F-FSR | 功能描述:电信线路管理 IC Si3050 FCC/TBR21 Voice DAA Line-Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| Si3011-F-FT | 功能描述:电信语音调制 IC Si3050 FCC/TBR21 Voice DAA Line-Side RoHS:否 制造商:Epson Electronics America 产品: 应用:Voice Guidance product 封装 / 箱体:PQFP-52 电源电压-最大:3.6 V, 5.5 V 最大工作温度: 最小工作温度: 封装: |
| SI3011-F-FTR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 FCC/TBR21 VOICE DAA LINE-SIDE - LEAD-FREE - Tape and Reel |
| SI3011-F-GM | 制造商:SILABS 制造商全称:SILABS 功能描述:PROGRAMMABLE VOICE DAA SOLUTIONS |
| SI3011-F-GS | 制造商:SILABS 制造商全称:SILABS 功能描述:PROGRAMMABLE VOICE DAA SOLUTIONS |
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