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| 型号： | SI3056-D-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 22/94页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM-SIDE DAA 16SOIC |
| 标准包装： | 48 |
| 数据格式： | V.92 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
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Si3056
Si3018/19/10
Rev. 1.05
29
There are two selections that are useful for satisfying
non-standard ac termination requirements. The 350
+
(1000
|| 210 nF) impedance selection is the ANSI/
EIA/TIA 464 compromise impedance network for trunks.
The last ac termination selection, ACIM[3:0] = 1111, is
designed to satisfy minimum return loss requirements
for every country in the world that requires a complex
termination. For any of the ac termination settings, the
programmable hybrid can be used to further reduce
near-end echo. See “5.13.Transhybrid Balance”
for
more details.
5.13. Transhybrid Balance
The Si3056 contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation. This hybrid circuit is adjusted for each ac
termination setting selected.
The Si3056 also offers a digital filter stage for additional
near-end echo cancellation. For each ac termination
setting selected, the eight programmable hybrid
registers (Registers 45-52) can be programmed with
coefficients to provide increased cancellation of real-
world line anomalies. This digital filter can produce
10 dB or greater of near-end echo cancellation in
addition to the echo cancellation provided by the analog
hybrid circuitry.
5.14. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3056 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “5.21.Caller ID” on
page 32. The ring detection threshold is programmable
with the RT bit (Register 16, bit 0). The ring detector
output can be monitored in three ways. The first method
uses the RGDT pin. The second method uses the
register bits, RDTP, RDTN, and RDT (Register 5). The
final method uses the DTX output.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
setting the RPOL bit (Register 14, bit 1). This pin is a
standard CMOS output. If multiple RGDT pins are
connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k
.
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RDT bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to 0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the AOUT/INT pin when RDT is triggered. This interrupt
can
be
cleared
by
writing
to
the
RDTI
bit
(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is
set, an interrupt occurs on both the beginning and end
of the ring pulse. Ring validation may be enabled when
using the RDI bit.
The third method to monitor detection uses the DTX
data
samples
to
transmit
ring
data.
If
the
communications link is active (PDL = 0) and the device
is not off-hook or in on-hook line monitor mode, the ring
data is presented on DTX. The waveform on DTX
depends on the state of the RFWE bit.
When RFWE is 0, DTX is –32768 (0x8000) while the
RNG1-RNG2 voltage is between the thresholds. When
a ring is detected, DTX transitions to +32767 when the
ring signal is positive, then goes back to –32768 when
the ring is near 0 and negative. Thus a near square
wave is presented on DTX that swings from –32768 to
+32767 in cadence with the ring signal.
When RFWE is 1, DTX sits at approximately +1228
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3056-D-FSR | 功能描述:电信线路管理 IC Si3056 DAA System Side SSI Interface RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3056-D-ZS3R | 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET 56KBPS - Tape and Reel |
| SI3056-F-FS | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3056-FS | 功能描述:IC SYSTEM-SIDE DAA 16SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 调制解调器 - IC 和模块 系列:- 标准包装:25 系列:- 数据格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 电源电压:3.3V 安装类型:- 封装/外壳:- 供应商设备封装:- 包装:托盘 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名称:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
| SI3056-FSR | 制造商:Silicon Laboratories Inc 功能描述:SI3056 DAA SYSTEM-SIDE, SSI INTERFACE - LEAD-FREE SOIC 0 TO - Tape and Reel |
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