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| 型号： | SI3056-D-FS |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 35/94页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM-SIDE DAA 16SOIC |
| 标准包装： | 48 |
| 数据格式： | V.92 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC N |
| 包装： | 管件 |
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Si3056
Si3018/19/10
40
Rev. 1.05
passes through the internal filters and transmitted on
SDO which introduces approximately 0.9 dB of
attenuation on the SDI signal received. The group delay
of both transmit and receive filters exists between SDI
and SDO. Clearing the PDL bit disables this mode and
the SDO data is switched to the receive data from the
line-side. When the PDL bit is cleared, the FDT bit
(Register 12, bit 6) becomes active, indicating the
successful communication between the line-side and
DSP-side. This can be used to verify that the isolation
link is operational.
The digital data loop-back mode offers a way to input
data on the SDI pin and have the identical data be
output on the SDO pin by bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
enables this mode. No line-side power or off-hook
sequence is required for this mode. The digital data
loopback mode is useful to verify communication
between the host processor/DSP and the DAA.
The remaining test modes require an off-hook sequence
to operate. The following sequence describes the off-
hook procedure required for the following test modes:
1. Powerup or reset.
2. Program the clock generator to the chosen sample
rate.
3. Enable line-side by clearing the PDL bit.
4. Issue an off-hook command.
5. Delay 402.75 ms to allow calibration to occur.
6. Set the desired test mode.
In the communications link loopback mode, the host
sends a digital input test pattern on SDI and receives
that digital test pattern back on SDO. To enable this
mode, set the IDL bit (Register 1, bit 1). In this mode,
the communication link is tested. The digital stream is
delivered across the isolation capacitors, C1 and C2 of
Figure 16 on page 17, to the line-side device and
returned across the same interface. In this mode, the
0.9 dB attenuation and filter group delays also exist.
The final testing mode, internal analog loopback, allows
the system to test the operation of the transmit and
receive paths through the line-side device and the
external components shown in Figure 16 on page 17. In
this test mode, the host provides a digital test waveform
on SDI. This data passes across the communications
link, is transmitted to and received from the line, passes
back across the communications link, and is presented
to the host on SDO. To enable this mode, clear the HBE
bit (Register 2, bit 1).
When the HBE bit is cleared, this causes a dc offset that
affects the signal swing of the transmit signal. Silicon
Laboratories recommends that the transmit signal be
12 dB lower than normal transmit levels. A lower level
eliminates clipping from the dc offset that results from
disabling the hybrid. It is assumed in this test that the
line ac impedance is nominally 600
.
Note:
All test modes are mutually exclusive. If more than one
test mode is enabled concurrently, the results are
unpredictable.
5.31. Exception Handling
The Si3056 provides several mechanisms to determine
if an error occurs during operation. Through the
secondary frames of the serial link, the controlling
systems can read several status bits.
The bit of highest importance is the frame detect bit
(FDT, Register 12, bit 6), which indicates that the
system-side (Si3056) and line-side devices are
communicating.
During normal operation, the FDT bit can be checked
before reading bits for information about the line-side. If
FDT is not set, the following bits related to the line-side
are invalid—RDT, RDTN, RDTP, LCS[4:0], LSID[1:0],
REVB[3:0], LCS2[7:0], LVS[7:0], ROV, BTD, DOD, and
OVL; the RGDT operation is also non-functional.
Following Powerup and reset, the FDT bit is not set
because the PDL bit (Register 6 bit 4) defaults to 1. The
communications link does not operate and no
information about the line-side can be determined. The
user must program the clock generator to a valid
configuration for the system and clear the PDL bit to
activate the communications link. As the system- and
line-side devices are establishing communication, the
system-side device does not generate FSYNC signals.
Establishing communication takes less than 10 ms.
Therefore, if the controlling DSP serial interface is
interrupt driven based on the FSYNC signal, the
controlling DSP does not require a special delay loop to
wait for this event to complete.
The FDT bit also can indicate if the line-side device
executes an off-hook request successfully. If the line-
side device is not connected to a phone line, the FDT bit
remains cleared. The controlling DSP must provide
sufficient time for the line-side to execute the off-hook
request. The maximum time for FDT to be valid
following an off-hook request is 10 ms. If the FDT bit is
high, the LCS[4:0] bits indicate the amount of loop
current flowing. If the FDT fails to be set following an off-
hook request, the PDL bit (Register 6) must be set high
for at least 1 ms to reset the line-side.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3056-D-FSR | 功能描述:电信线路管理 IC Si3056 DAA System Side SSI Interface RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3056-D-ZS3R | 制造商:Silicon Laboratories Inc 功能描述:MODEM CHIP CHIPSET 56KBPS - Tape and Reel |
| SI3056-F-FS | 制造商:Silicon Laboratories Inc 功能描述: |
| SI3056-FS | 功能描述:IC SYSTEM-SIDE DAA 16SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 调制解调器 - IC 和模块 系列:- 标准包装:25 系列:- 数据格式:V.21，V.22，V.23，V.29，V.32，V.34，V.90，V.92，Bell 103，Bell 212A 波特率:33.6k 电源电压:3.3V 安装类型:- 封装/外壳:- 供应商设备封装:- 包装:托盘 配用:591-1013-ND - KIT DEV SOCKETMODEM PARALLEL591-1009-ND - KIT DEV SRL SOCKETMODEM UNIVERSL 其它名称:MT5656SMI-P-V-34.R2-SPMT5656SMI-P-V-34.R2-SP-NDQ4711574 |
| SI3056-FSR | 制造商:Silicon Laboratories Inc 功能描述:SI3056 DAA SYSTEM-SIDE, SSI INTERFACE - LEAD-FREE SOIC 0 TO - Tape and Reel |
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