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| 型号： | SI3402ISO-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 11/22页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL POE ISOL FOR SI3402 |
| 标准包装： | 1 |
| 主要目的： | 特殊用途 DC/DC，以太网供电（POE） |
| 输出及类型： | 1，隔离 |
| 输出电压： | 5V |
| 输入电压： | 44 ~ 57 V |
| 稳压器拓扑结构： | 回扫 |
| 频率 - 开关： | 350kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | Si3402 |
| 其它名称： | 336-1828 |
Si3402
Table 9. Hotswap Interface Modes
As an added benefit, the transient surge suppressor,
when tripped, actively disables the hotswap interface
Input Voltage
(|CT1-CT2| or |SP1-SP2|)
0 to 2.7 V
2.7 to 11 V
11 to 14 V
14 to 22 V
22 to 42 V
42 up to 57 V
57 down to 36 V
Si3402 Mode
Inactive
Detection signature
Detection turns off and
internal bias starts
Classification signature
Transition region
Switcher operating mode
(hysteresis limit based on
rising input voltage)
Switcher operating mode
(hysteresis limit based on
falling input voltage)
and switching regulator, preventing downstream circuits
from encountering the high-energy transients.
3.2.2. Detection
In order to identify a device as a valid PD, a PSE will
apply a voltage in the range of 2.8 to 10 V on the cable
and look for the 25.5 k ? signature resistor. The Si3402
will react to voltages in this range by connecting an
external 25.5 k ? resistor between VPOS and VNEG.
This external resistor and internal low-leakage control
circuitry create the proper signature to alert the PSE
that a valid PD has been detected and is ready to have
power applied. The internal hotswap switch is disabled
during this time to prevent the switching regulator and
attached load circuitry from generating errors in the
detection signature.
Since the Si3402 integrates the diode bridges, the IC
can compensate for the voltage and resistance effects
3.2.1. Rectification Diode Bridges and
Surge Suppressor
The 802.3 specification defines the input voltage at the
RJ-45 connector of the PD with no reference to polarity.
In other words, the PD must be able to accept power of
either polarity at each of its inputs. This requirement
necessitates the use of two sets of diode bridges, one
for the CT1 and CT2 pins and one for the SP1 and SP2
pins to rectify the voltage. Furthermore, the standard
requires that a PD withstand a high-voltage transient
surge consisting of a 1000 V common-mode impulse
with 300 ns rise time and 50 μs half fall time. Typically,
the diode bridge and the surge suppressor have been
implemented externally, adding cost and complexity to
the PD system design.
The diode bridge* and the surge suppressor have been
integrated into the Si3402, thus reducing system cost
and design complexity.
*Note: Silicon Laboratories recommends that on-chip diode
bridges be bypassed when >7 W of output power is
required.
By integrating the diode bridges, the Si3402 gains
access to the input side of the diode bridge. Monitoring
the voltage at the input of the diode bridges instead of
the voltage across the load capacitor provides the
earliest indication of a power loss. This true early power
loss indicator, PLOSS, provides a local microcontroller
time to save states and shut down gracefully before the
load capacitor discharges below the minimum 802.3-
specified operating voltage of 36 V. Integration of the
surge suppressor enables optimization of the clamping
voltage and guarantees protection of all connected
circuitry.
of the diode bridges. The 802.3 specification requires
that the PSE use a multi-point, ? V/ ? I measurement
technique to remove the diode-induced dc offset from
the signature resistance measurement. However, the
specification does not address the diode's nonlinear
resistance and the error induced in the signature
resistor measurement. Since the diode's resistance
appears in series with the signature resistor, the PD
system must find some way of compensating for this
error. In systems where the diode bridges are external,
compensation is difficult and suffers from errors. Since
the diode bridges are integrated in the Si3402, the IC
can compensate for this error by offsetting resistance
across all operating conditions and thus meeting the
802.3 requirements. An added benefit is that this
function can be tested during the IC’s automated testing
step, guaranteeing system compliance when used in
the final PD application. For more information about
supporting higher-power applications (above 12.95 W),
see “AN313: Using the Si3402 in High Power
Applications” and “AN314: Power Combining Circuit for
PoE for up to 18.5 W Output”.
3.2.3. Classification
Once the PSE has detected a valid PD, the PSE may
classify the PD for one of five power levels or classes. A
class is based on the expected power consumption of
the powered device. An external resistor sets the
nominal class current that can then be read by the PSE
to determine the proper power requirements of the PD.
When the PSE presents a fixed voltage between 15.5 V
and 20.5 V to the PD, the Si3402 asserts the class
current from VPOS through the RCL resistor. The
resistor values associated with each class are shown in
Table 10.
Rev. 1.31
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3403-A-GM | 制造商:Silicon Laboratories Inc 功能描述:POE POWERED DEVICE (UP TO 17W, LOW-EMI) - RECOMMENDED FOR AL - Trays 制造商:Silicon Laboratories Inc 功能描述:IC POE CTLR TO 17W LOW EMI 20QFN 制造商:Silicon Laboratories Inc 功能描述:PoE Powered Device (up to 17W, low-EMI) |
| Si3403-A-GMR | 制造商:Silicon Laboratories Inc 功能描述:POE POWERED DEVICE (UP TO 17W, LOW-EMI) - RECOMMENDED FOR AL - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:PoE Powered Device (up to 17W, low-EMI) |
| SI3403DV-T1-E3 | 功能描述:MOSFET 20V 5.0A 3.2W RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI3403DV-T1-GE3 | 功能描述:MOSFET 20V 5.0A 3.2W 70mohm @ 4.5V RoHS:否 制造商:STMicroelectronics 晶体管极性:N-Channel 汲极/源极击穿电压:650 V 闸/源击穿电压:25 V 漏极连续电流:130 A 电阻汲极/源极 RDS（导通）:0.014 Ohms 配置:Single 最大工作温度: 安装风格:Through Hole 封装 / 箱体:Max247 封装:Tube |
| SI3407DV | 制造商:VISHAY 制造商全称:Vishay Siliconix 功能描述:P-Channel 20-V (D-S) MOSFET |
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