参数资料
型号: SI3402ISO-EVB
厂商: Silicon Laboratories Inc
文件页数: 17/22页
文件大小: 0K
描述: BOARD EVAL POE ISOL FOR SI3402
标准包装: 1
主要目的: 特殊用途 DC/DC,以太网供电(POE)
输出及类型: 1,隔离
输出电压: 5V
输入电压: 44 ~ 57 V
稳压器拓扑结构: 回扫
频率 - 开关: 350kHz
板类型: 完全填充
已供物品: 板,CD
已用 IC / 零件: Si3402
其它名称: 336-1828
Si3402
6. Recommended Land Pattern
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Figure 6. Si3402 Recommended Land Pattern
Table 13. PCB Land Pattern Dimensions
Symbol
P1
P2
X1
Y1
C1
C2
E
Min
2.70
2.70
0.25
0.90
Nom
2.75
2.75
0.30
0.95
4.70
4.70
0.80
Max
2.80
2.80
0.35
1.00
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
4. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 μm minimum, all the way around the pad.
Stencil Design
5. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
6. The stencil thickness should be 0.125 mm (5 mils).
7. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
8. A 2x2 array of 1.2 mm square openings on 1.4 mm pitch should be used for the center ground pad.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.31
17
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