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| 型号： | SI4126M-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/34页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR SI4126 |
| 标准包装： | 1 |
| 类型： | 合成器 |
| 适用于相关产品： | SI4126 |
| 已供物品： | 板，CD |
| 其它名称： | 336-1112 |
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Si4136/Si4126
18
Rev. 1.41
programmed independently. Programming either the R-
or N-Divider register for RF1 or RF2 automatically
selects the associated output.
When XINDIV2 = 0, the reference frequency on the XIN
pin is divided by R and this signal is the input to the
PLL’s phase detector. The other input to the phase
detector is the PLL’s VCO output frequency divided by
2N for the RF PLLs or N for the IF PLL. After an initial
transient
Equation 1. fOUT = (2N/R) fREF (for the RF PLLs)
Equation 2. fOUT = (N/R) fREF (for the IF PLL).
The integers R are set by programming the RF1 R-
Divider register (Register 6), the RF2 R-Divider register
(Register 7) and the IF R-Divider register (Register 8).
The integers N are set by programming the RF1 N-
Divider register (register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
If the optional divide-by-2 circuit on the XIN pin is
enabled (XINDIV2 = 1) then after an initial transient
fOUT = (N/R) fREF (for the RF PLLs)
fOUT = (N/2R) fREF (for the IF PLL).
Each N-Divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the control of these
sub-circuits
is
handled
automatically.
Only
the
appropriate N value should be programmed.
2.5. PLL Loop Dynamics
The transient response for each PLL is determined by
its phase detector update rate f (equal to fREF/R) and
the phase detector gain programmed for each RF1,
RF2, or IF synthesizer. (See Register 1.) Four different
settings for the phase detector gain are available for
each PLL. The highest gain is programmed by setting
the two phase detector gain bits to 00, and the lowest by
setting the bits to 11. The values of the available gains,
relative to the highest gain, are listed in Table 7.
In general, a higher phase detector gain will decrease
in-band phase noise and increase the speed of the PLL
transient until the point at which stability begins to be
compromised. The optimal gain depends on N. Table 8
lists recommended settings for different values of N.
The VCO gain and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period T (T equals 1/f).
During the first 13 update periods the Si4136 executes
the self-tuning algorithm. Thereafter the PLL controls
the
output
frequency.
Because
of
the
unique
architecture of the Si4136 PLLs, the time required to
settle the output frequency to 0.1 ppm error is only
about 25 update periods. Thus, the total time after
power-up or a change in programmed frequency until
the synthesized frequency is well settled—including
time for self-tuning—is around 40 update periods.
Note: This settling time analysis holds for f 500 kHz. For
f 500 kHz, the settling time can be a maximum of
100
s as specified in Table 5.
2.6. RF and IF Outputs (RFOUT and IFOUT)
The RFOUT and IFOUT pins are driven by amplifiers
that buffer the RF VCOs and IF VCO, respectively. The
RF output amplifier receives its input from either the
RF1 or RF2 VCO, depending upon which R- or N-
Divider
register
was
last
written.
For
example,
programming
the
N-Divider
register
for
RF1
automatically selects the RF1 VCO output.
Figure 13 on page 15 shows an application diagram for
the Si4136. The RF output signal must be AC coupled
to its load through a capacitor.
The IFOUT pin must also be AC coupled to its load
through a capacitor. The IF output level is dependent
upon the load. Figure 17 displays the output level
versus load resistance. For resistive loads greater than
500
the output level saturates and the bias currents in
the IF output amplifier are higher than they need to be.
The LPWR bit in the Main Configuration register
Table 7. Gain Values (Register 1)
KP Bits
Relative P.D.
Gain
00
1
01
1/2
10
1/4
11
1/8
Table 8. Optimal KP Settings
N
RF1
KP1<1:0>
RF2
KP2<1:0>
IF
KPI<1:0>
2047
00
2048 to 4095
00
01
4096 to 8191
01
10
8192 to 16383
10
11
16384
11
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