参数资料
型号: SI4421-A0-FT
厂商: Silicon Laboratories Inc
文件页数: 20/45页
文件大小: 0K
描述: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
数据传输率 - 最大: 256kbps
调制或协议: FSK
应用: ISM
功率 - 输出: 7dbm
灵敏度: -110dBm
电源电压: 2.2 V ~ 3.8 V
电流 - 接收: 15mA
电流 - 传输: 28mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1737-5
Si4421
Bits 2-0 ( f2 to f0 ):
DQD threshold parameter.
The Data Quality Detector is a digital processing part of the radio, connected to the demodulator - it is an indicator
reporting the reception of an FSK modulated RF signal. It will work every time the receiver is on. Setting this
parameter defines how clean incoming data stream would be stated as good data (valid FSK signal).
If the internally calculated data quality value exceeds the DQD threshold parameter for five consecutive data bits
for both the high and low periods, then the DQD signal goes high.
The DQD parameter in the Data Filter Command should be chosen according to the following rules:
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The DQD parameter can be calculated with the following formula:
DQD par = 4 x (deviation – TX-RX offset ) / bit rate
It should be larger than 4 because otherwise noise might be treated as a valid FSK signal
The maximum value is 7.
7. FIFO and Reset Mode Command
Bit
15
1
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
f3
6
f2
5
f1
4
f0
3
sp
2
al
1
ff
0
dr
POR
CA80h
Bits 7-4 ( f3 to f0 ):
Bit 3 ( sp ):
FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Select the length of the synchron pattern:
sp
0
1
Byte1
2Dh
Not used
Byte0 (POR)
D4h
D4h
Synchron Pattern (Byte1+Byte0)
2DD4h
D4h
Note: The synchron pattern consists of one or two bytes depending on the sp bit. Byte1 is fixed 2Dh, Byte0 can be programmed by
the Synchron Pattern Command (page 21).
Bit 2 ( al ):
Set the input of the FIFO fill start condition:
al
0
1
FIFO fill start condition
Synchron pattern
Always fill
20
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