参数资料
型号: SI4421-A0-FT
厂商: Silicon Laboratories Inc
文件页数: 31/45页
文件大小: 0K
描述: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
数据传输率 - 最大: 256kbps
调制或协议: FSK
应用: ISM
功率 - 输出: 7dbm
灵敏度: -110dBm
电源电压: 2.2 V ~ 3.8 V
电流 - 接收: 15mA
电流 - 传输: 28mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1737-5
Si4421
RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16-bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from
being filled with noise and overloading the external microcontroller.
Interrupt Controlled Mode:
The user can define the FIFO IT level (the number of received bits) which will generate the nFFIT when exceeded. The status bits
report the changed FIFO status in this case.
Polling Mode:
When nFFS signal is low the FIFO output is connected directly to the SDO pin and its content can be clocked out by the SCK. Set the
FIFO IT level to 1. In this case, as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away.
When FFIT goes low, no more bits need to be taken.
An SPI read command is also available to read out the content of the FIFO ( Receiver FIFO Read Command , page 21).
FIFO Read Example with FFIT Polling
nSEL
0
1
2
3
4
SCK
nFFS
FIFO read out
SDO
FIFO OUT
FO+1
FO+2
FO+3
FO+4
FFIT
Note: During FIFO access f SCK cannot be higher than f ref /4, where f ref is the crystal oscillator frequency. When the duty-cycle of the
clock signal is not 50% the shorter period of the clock pulse should be at least 2/f ref .
RECOMMENDED PACKET STRUCTURES
Preamble
Synchron word
(Can be network ID)
Payload
CRC
Minimum length
Recommended length
4 - 8 bits (1010b or 0101b)
8 -12 bits (e.g. AAh or 55h)
D4h (programmable)
2DD4h (D4 is programmable)
?
?
4 bit - 1 byte
2 byte
31
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