参数资料
型号: SI4421-A0-FT
厂商: Silicon Laboratories Inc
文件页数: 21/45页
文件大小: 0K
描述: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
数据传输率 - 最大: 256kbps
调制或协议: FSK
应用: ISM
功率 - 输出: 7dbm
灵敏度: -110dBm
电源电压: 2.2 V ~ 3.8 V
电流 - 接收: 15mA
电流 - 传输: 28mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1737-5
Si4421
Bit 1 ( ff ):
FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 ( dr ): Disables the highly sensitive RESET mode.
dr
0
1
Reset mode
Sensitive reset
Non-sensitive reset
Reset triggered when
V dd below 1.6V, V dd glitch greater than 600mV
V dd below 250mV
Note: To restart the synchron pattern recognition, bit 1 ( ef , FIFO fill enable) should be cleared and set.
8. Synchron Pattern Command
Bit
15
1
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
b7
6
b6
5
b5
4
b4
3
b3
2
b2
1
b1
0
b0
POR
CED4h
The Byte0 of the synchron pattern (see FIFO and Reset Mode command , page 20) can be reprogrammed by B < b7 : b0 >.
9. Receiver FIFO Read Command
Bit
15
1
14
0
13
1
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command
(page 15) .
Note: During FIFO access f SCK cannot be higher than f ref /4, where f ref is the crystal oscillator frequency. When the duty-cycle of the
clock signal is not 50 % the shorter period of the clock pulse width should be at least 2/f ref .
10. AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
a1
6
a0
5
rl1
4
rl0
3
st
2
fi
1
oe
0
en
POR
C4F7h
Bit 7-6 ( a1 to a0 ):
Automatic operation mode selector:
a1
0
0
1
1
a0
0
1
0
1
Operation mode
Auto mode off (Strobe is controlled by microcontroller)
Runs only once after each power-up
Keep the f offset only during receiving (VDI=high)
Keep the f offset value independently from the state of the VDI signal
21
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