参数资料
型号: SI4421-A0-FT
厂商: Silicon Laboratories Inc
文件页数: 4/45页
文件大小: 0K
描述: IC TXRX FSK 915MHZ 3.8V 16-TSSOP
标准包装: 96
频率: 433MHz,868MHz,915MHz
数据传输率 - 最大: 256kbps
调制或协议: FSK
应用: ISM
功率 - 输出: 7dbm
灵敏度: -110dBm
电源电压: 2.2 V ~ 3.8 V
电流 - 接收: 15mA
电流 - 传输: 28mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
包装: 管件
产品目录页面: 585 (CN2011-ZH PDF)
其它名称: 336-1737-5
Si4421
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
SDI
SCK
nSEL
SDO
nIRQ
FSK
DATA
nFFS
DLCK
CFIL
FFIT
CLK
XTL
REF
nRES
VSS
RF2
RF1
VDD
ARSSI
nINT
VDI
Type
DI
DI
DI
DO
DO
DI
DO
DI
DO
AIO
DO
DO
AIO
AIO
DIO
S
AIO
AIO
S
AO
DI
DO
Function
Data input of the serial control interface
Clock input of the serial control interface
Chip select input of the serial control interface (active low)
Serial data output with bus hold
Interrupt request output (active low)
Transmit FSK data input (internal pull up resistor 133 k)
Received data output (FIFO not used)
FIFO select input (active low). In FIFO mode, when bit ef is set in Configuration Setting Command ,
page 15 (internal pull up resistor 133 k)
Received data clock output (Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
FIFO interrupt (active high). In FIFO mode, when bit ef is set in Configuration Setting Command
Microcontroller clock output
Crystal connection (the other terminal of crystal to VSS) or external reference input
External reference input. Use 33 pF series coupling capacitor
Open drain reset output with internal pull-up and input buffer (active low)
Ground reference voltage
RF differential signal input/output
RF differential signal input/output
Positive supply voltage
Analog RSSI output
Interrupt input (active low)
Valid data indicator output
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the transceiver.
4
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