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参数资料
| 型号： | SI5100-H-GL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 28/40页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195PBGA |
| 标准包装： | 119 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 195-LBGA |
| 供应商设备封装： | 195-BGA（15x15） |
| 包装： | 托盘 |
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Si5100
34
Rev. 1.5
M9
TXMSBSEL
I
LVTTL
Transmit Data Bus Bit Order Select.
This input determines the order in which data
bits received on the TXDIN[15:0] bus are trans-
mitted on the high-speed serial output TXDOUT.
For TXMSBSEL = 0, data on TXDIN0 is trans-
mitted first followed by TXDIN1 through
TXDIN15 (TXDIN1 through TXDOUT3 if
MODE16 = 0).
For TXMSBSEL = 1, TXDIN15 (TXDIN3) is
transmitted first followed by TXDIN14 (TXDIN2)
through TXDIN0.
Note: This input has an internal pulldown.
L3
TXREXT
Transmitter External Bias Resistor.
This resistor is used by the transmitter circuitry
to establish bias currents within the device. This
pin must be connected to GND through a
3.09 k
1resistor.
M12
TXSQLCH
I
LVTTL
Transmit Data Squelch.
When TXSQLCH is set low, the output data
stream on TXDOUT is forced to a zero state. Set
TXSQLCH high for normal operation.
The TXSQLCH input is ignored when operating
in line loopback mode (LLBK = 0).
Note: This input has an internal pullup.
E5–10, F5–10,
G5–10, H5–10,
J5–10, K5–10
VDD
1.8 V
Supply Voltage.
Nominally 1.8 V.
H3
VDDIO
1.8 V or 3.3 V
LVTTL I/O Supply Voltage.
Connect to either 1.8 or 3.3 V. When connected
to 3.3 V, LVTTL compatible voltage swings are
supported on the LVTTL inputs and LVTTL out-
puts of the device.
C5
VREF
O
Voltage Ref
Voltage Reference.
The Si5100 provides an output voltage reference
that can be used by an external circuit to set the
LOS threshold, slicing level, or sampling phase
adjustment. The equivalent resistance between
this pin and GND should not be less than 10 k
.
The reference voltage is nominally 1.25 V.
Pin Number(s)
Name
I/O
Signal Level
Description
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