参数资料
| 型号： | SIC413CB-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 11/18页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 8SOIC |
| 标准包装： | 1 |
| 系列： | microBUCK® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 13.2 V |
| 输入电压： | 4.75 V ~ 26 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -25°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC |
| 其它名称： | SIC413CB-T1-E3DKR |
SiC413
Vishay Siliconix
Compensation Considerations
The criterion for unconditional stability of a closed loop
system is that the open loop transfer function has the
following attributes.
1. The magnitude of the open loop transfer function must
cross through 0 dB with a slope of - 20 dB per decade
This output filter configuration can be challenging because
there is no zero to help boost the phase shift that is
introduced by the LC double pole.
Case 3: All capacitors have ESR, no ceramics.
Ignoring C4 we have the following for the poles and zero
2. The phase shift of the open loop transfer function must be
at least 45 at the frequency, at which the magnitude of the
f P1,P2,ESR =
2 π
1
L1 ? C5
loop gain crosses through 0 dB
3. The phase shift should not be rapidly decreasing at loop
gain slightly less than 0 dB
To determine if these criterion are met the Bode plot of the
transfer function is drawn. Before drawing the bode plot, the
f P3,ESR
f Z1,ESR =
does not exist
1
2 π ? C5 ? R6
poles and zeros need to be located. The following discussion
serves as a guide to selection of the component values for
the compensation network.
The compensation process begins by selecting loop
bandwidth. We recommend that the 0 dB crossover
frequency is set somewhere between 10 % and 20 % of
switching frequency. The SiC413CB has a fixed switching
This case is the best situation for loop compensation since
no extra pole to add phase shift. The zero created with the
ESR also helps reverse phase shift added by the LC filter.
In the output voltage feedback network block there is one
pole (denoted P4) and one zero (denoted Z2). The locations
of the pole and zero are
frequency of 500 kHz. This means that the bandwidth of the
loop can be set somewhere between 50 kHz and 100 kHz.
This wide loop bandwidth, made possible by the ultra fast
f P4 =
2 π ?
1
R1 ? R2
R1 + R2
? C1
=
1
2 π ? C1 ? (R1//R2)
error amplifier in the SiC413CB, can provide excellent
transient response and load regulation.
f Z2 =
1
2 π ? C1 ? R1
V O = (1 + R1 ) ? V REF
It can be seen that within the LC filter block, there are
generally three poles (denoted P1, P2 and P3) and one zero
(denoted Z1). The double pole (P1 and P2) created by the
LC filter is the dominant response characteristic of the
system. The locations of these poles and zero depend
strongly on the types of capacitors used in the output filter.
Three cases will be analyzed as follows.
Case 1: Output capacitors are a combination of those with
ESR (C5. e.g. polymer or tantalum type) and those with no
ESR or little ESR (C4. e.g. ceramic type)
The poles and zero for this case are as follows
In this block C1 and R1 create the zero and C1 together with
the parallel combination of R1 and R2 generates the pole.
Adding a capacitor in parallel with R2 is not effective here. It
does not change the zero location and move the pole closer
to this zero and cancels out its effect on phase margin.
From Figure 4 we can derive the DC expression for the
output voltage.
R2
From this equation and the equations of the pole and zero
f P1,P2 ≈
2 π
1
L1 ? (C4 + C5)
locations, it can be seen that pole and zero locations of this
block have the following relationship
f P4 V O
f P3 ≈
f Z1 ≈
1
2 π ? C4 ? R6
1
2 π ? C5 ? R6
=
f Z2 V REF
This relationship means that when the output voltage V O is
To meet the above stability criterion, the frequency of the
zero f Z1 should be placed at a frequency lower than or equal
to that at the double pole of f P1,P2 . Pole f P3 should be located
at a much higher frequency than f P1,P2 . This requirement
sets the boundaries on the values of C4, C5 and R6.
Capacitor C4 has to be much smaller than C5.
Case 2: Output capacitor is all ceramic MLCC
Ignoring C5 and R6, the poles are as follows
approaching the chip reference voltage, V REF , the zero in the
sampling network has diminishing effect on boosting the loop
phase margin. In other words, the value if adding C1 is more
apparent when the output voltage is high relative to V REF and
becomes smaller at lower output voltages. Therefore, the
use of this capacitor is optional for low voltage conversions
(e.g. 1.2 V output or lower).
To make the zero f Z2 work for compensation of the control
loop it should to be placed at a frequency that is less than or
equal to the frequency of the LC double pole location.
f P1,P2, MLCC =
2 π
1
L1 ? C4
Block 3 is a DC transfer block and therefore has no pole and
zero. It only affects the DC gain of open loop transfer
function. This can affect phase margin as increasing the DC
f P3, MLCC
and
f Z1, MLCC
w ill not exist
loop gain can increase the loop bandwidth and reduce phase
margin and visa versa.
Document Number: 69057
S09-2250-Rev. D, 26-Oct-09
www.vishay.com
11
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