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| 型号： | SIC424CD-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 44MLP-28 |
| 标准包装： | 1 |
| 系列： | microBUCK® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 5.5 V |
| 输入电压： | 3 V ~ 28 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-MLPQ（4x4） |
| 其它名称： | SIC424CD-T1-GE3DKR |
SiC414, SiC424
Vishay Siliconix
two voltages are within ± 300 mV (typically) of each other,
within 32 cycles, the V LDO pin connects to the V OUT pin using
an internal switch, and the LDO is turned off.
In the second method, the DC/DC converter is already
running and the LDO is enabled. In this case the 32 cycles
are started as soon as the LDO reaches 90 % of its final
value. At this time, the V LDO and V OUT pins are compared,
and if within ± 300 mV (typically) the switch-over occurs and
the LDO is turned off.
threshold and stays above 1 V, then the switcher will turn off
but the LDO remains on. The V IN UVLO function has a typical
threshold of 2.6 V on the V IN rising edge.The falling edge
threshold is 2.4 V.
Note that it is possible to operate the switcher with the LDO
disabled, but the ENL pin must be below the logic low
threshold (0.4 V maximum). The table below summarizes the
function of the ENL and EN pins, with respect to the rising
edge of ENL.
Switch-Over Limitations on V OUT and V LDO
Because the internal switch-over circuit always compares
the V OUT and V LDO pins at start-up, there are voltage
limitations on permissible combinations of these pins.
Consider the situation where V OUT is programmed to 4.7 V.
After start-up, the device would connect V OUT to V LDO and
disable the LDO, since the two voltages are within the
± 300 mV switch-over window. To avoid unwanted switch-
EN
Low
High
Low
High
Low
High
ENL
Low, < 0.4 V
Low, < 0.4 V
High, < 2.6 V
High, < 2.6 V
High, > 2.6 V
High, > 2.6 V
LDO
Off
Off
On
On
On
On
Switcher
Off
On
Off
Off
Off
On
over, the minimum difference between the voltages for V OUT
and V LDO should be ± 500 mV.
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 10.
Figure 11 below shows the ENL voltage thresholds and their
effect on LDO and switcher operation.
S w itcho v er
control
V LDO
Parastic diode
V 5 V
S w itcho v er
MOSFET
V OUT
Parastic diode
Figure 10 - Switch-Over MOSFET Parasitic Diodes
There are some important design rules that must be followed
to prevent forward bias of these diodes. The following two
conditions need to be satisfied in order for the parasitic
diodes to stay off.
? V5V ? V LDO
? V5V ? V OUT
If either V LDO or V OUT is higher than V5V, then the respective
diode will turn on and the SiC414 and SiC424 operating
current will flow through this diode. This has the potential of
damaging the device.
ENL Pin and V IN UVLO
The ENL pin also acts as the switcher under-voltage lockout
for the V IN supply. The V IN UVLO voltage is programmable
via a resistor divider at the V IN , ENL, and A GND pins. ENL is
the enable/disable signal for the LDO. In order to implement
the V IN UVLO there is also a timing requirement that needs
to be satisfied. If the ENL pin transitions low within
2 switching cycles and is < 1 V, then the LDO will turn off, but
the switcher remains on. If ENL goes below the V IN UVLO
Figure 11 - ENL Thresholds
ENL Logic Control of PWM Operation
When the ENL input is driven above 2.6 V, it is impossible to
determine if the LDO output is going to be used to power the
device or not. In self-powered operation where the LDO will
power the device, it is necessary during the LDO start-up to
hold the PWM switching off until the LDO has reached 90 %
of the final value. This prevents overloading the current-
limited LDO output during the LDO start-up. However, if the
switcher was previously operating (with EN/PSV high but
ENL at ground, and V5V supplied externally), then it is
undesirable to shut down the switcher. To prevent this, when
the ENL input is above 2.6 V (above the V IN UVLO
threshold), the internal logic checks the P GOOD signal. If
P GOOD is high, then the switcher is already running and the
LDO will run through the start-up cycle without affecting the
switcher. If P GOOD is low, then the LDO will not allow any
PWM switching until the LDO output has reached 90 % of its
final value.
www.vishay.com
14
For technical questions, contact: powerictechsupport@vishay.com
Document Number: 63388
S13-0248-Rev. B, 04-Feb-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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