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参数资料
| 型号： | SIC424CD-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 44MLP-28 |
| 标准包装： | 1 |
| 系列： | microBUCK® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 5.5 V |
| 输入电压： | 3 V ~ 28 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-MLPQ（4x4） |
| 其它名称： | SIC424CD-T1-GE3DKR |
SiC414, SiC424
Vishay Siliconix
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 12. This capacitor should be left unpopulated
unless it can be confirmed that double-pulsing exists.
Adding the C TOP capacitor will couple more ripple into FB to
help eliminate the problem. An optional connection on the
PCB should be available for this capacitor.
C TOP
voltage across CL, analogous to the ramp voltage generated
across the ESR of a standard capacitor. This ramp is then
capacitive coupled into the FB pin via capacitor C C .
V OUT
R 1
R 2
To FB pin
Figure 13 - Virtual ESR Ramp Circuit
Figure 12 - Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
One simple way to solve this problem is to add trace
DUTY =
t O N (MI N )
t O N (MI N ) x t OFF(MAX)
resistance in the high current output path. A side effect of
adding trace resistance is a decrease in load regulation.
The inductor resistance and MOSFET on-state voltage drops
must be included when performing worst-case dropout
duty-factor calculations.
ESR Requirements
A minimum ESR is required for two reasons. One reason
is to generate enough output ripple voltage to provide
10 mV p-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications, the total
output ripple voltage is dominated by the output capacitors,
typically SP or POSCAP devices. For stability the ESR zero
of the output capacitor should be lower than approximately
one-third the switching frequency. The formula for minimum
ESR is shown by the following equation.
System DC Accuracy (V OUT Controller)
Three factors affect V OUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator off set is trimmed so that under static conditions
it trips when the feedback pin is 750 mV, 1 %.
The on-time pulse from the SiC414 and SiC424 in the design
example is calculated to give a pseudo-fixed frequency of
250 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because constant on-time converters regulate to the valley
of the output ripple, 1/2 of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with V IN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point. If the ripple increases to
ESR MI N =
3
2 x π x C OUT x f S W
80 mV with V IN = 25 V, then the measured DC output will be
40 mV above the comparator trip. The best way to minimize
this effect is to minimize the output ripple.
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
virtual ESR network composed of two capacitors and one
resistor, as shown in figure 12. This network creates a ramp
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of trace
resistance between the inductor and output capacitor. This
trace resistance should be optimized so that at full load the
output droops to near the lower regulation limit. Passive
Document Number: 63388
S13-0248-Rev. B, 04-Feb-13
For technical questions, contact: powerictechsupport@vishay.com
www.vishay.com
17
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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