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| 型号： | SIC424CD-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 16/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 44MLP-28 |
| 标准包装： | 1 |
| 系列： | microBUCK® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 5.5 V |
| 输入电压： | 3 V ~ 28 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-MLPQ（4x4） |
| 其它名称： | SIC424CD-T1-GE3DKR |
SiC414, SiC424
Vishay Siliconix
t O N _ V I N MI N =
25 pF x R tO N x V OUT
V I N MI N
+ 10 ns = 311 ns
load dI/dt is not much faster than the - dI/dt in the inductor,
then the inductor current will tend to track the falling load
current. This will reduce the excess inductive energy that
I RIPPLE =
( V I N - V OUT ) x t O N
L
must be absorbed by the output capacitor, therefore a
smaller capacitance can be used.
I RIPPLE_ V I N MI N =
(10. 8 - 1 V ) x 311 ns
1.5 μ H
= 2.03 A
The following can be used to calculate the needed
capacitance for a given dI LOAD /dt:
Capacitor Selection
The output capacitors are chosen based on required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. Change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal is for the output voltage regulation to be
Peak inductor current is shown by the next equation.
I LPK = I MAX + 1/2 x I RIPPLEMAX
I LPK = 10 + 1/2 x 2.53 = 7.26 A
Rate of change of load current = dI LOAD /dt
I MAX = maximum load release = 6 A
I LPK I MAX
± 4 % under static conditions. The internal 750 mV reference
tolerance is 1 %. Assuming a 1 % tolerance from the FB
resistor divider, this allows 2 % tolerance due to V OUT ripple.
C OUT = I LPK x
L x - x dt
V OUT dl LOAD
2 ( V PK - V OUT )
Since this 2 % error comes from 1/2 of the ripple voltage, the
allowable ripple is 4 %, or 40 mV for a 1 V output.
The maximum ripple current of 2.53 A creates a ripple
voltage across the ESR. The maximum ESR value allowed
Example
Load
dl LOAD
dt
=
1 .25 A
1 μ s
is shown by the following equations.
This causes the output current to move from 6 A to 0 A in
ESR MAX =
V RIPPLE
I RIPPLEMAX
=
40 m V
2.53 A
4.8 μs, giving the minimum output capacitance requirement
shown in the following equation.
ESR MAX = 15. 8 m Ω
C OUT = 7.26 x
7.26 6A
1.5 μ H x - x 1 μ s
1 V 1.25 A
2 (1.05 V - 1 V )
The output capacitance is chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is
at the peak, determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero in < 1 μs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
C OUT = 443 μ F
Note that C OUT is much smaller in this example, 443 μF
compared to 772 μF based on a worst-case load release. To
meet the two design criteria of minimum 443 μF and
maximum 15 m ? ESR, select two capacitors rated at 220 μF
and 15 m ? ESR or less.
It is recommended that an additional small capacitor be
x I RIPPLEMAX ) 2
L (I OUT +
C OUT_MI N =
1
2
( V PEAK ) 2 - ( V OUT ) 2
placed in parallel with C OUT in order to filter high frequency
switching noise.
Stability Considerations
Assuming a peak voltage V PEAK of 1.150 (100 mV rise
upon load release), and a 6 A load release, the required
capacitance is shown by the next equation.
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
x 2.53) 2
C OUT_MI N =
1
1.5 μ H (6 A +
2
(1.05) 2 - (1 V ) 2
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the minimum
off-time has expired. In extreme cases the noise can cause
C OUT_MI N = 772 μ F
If the load release is relatively slow, the output capacitance
can be reduced. At heavy loads during normal switching,
when the FB pin is above the 750 mV reference, the DL
output is high and the low-side MOSFET is on. During this
time, the voltage across the inductor is approximately - V OUT .
This causes a down-slope or falling dI/dt in the inductor. If the
three or more successive on-times. Double-pulsing will result
in higher ripple voltage at the output, but in most applications
it will not affect operation. This form of instability can usually
be avoided by providing the FB pin with a smooth, clean
ripple signal that is at least 10 mV p-p , which may dictate the
need to increase the ESR of the output capacitors. It is also
imperative to provide a proper PCB layout as discussed in
the Layout Guidelines section.
www.vishay.com
16
For technical questions, contact: powerictechsupport@vishay.com
Document Number: 63388
S13-0248-Rev. B, 04-Feb-13
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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