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参数资料
| 型号： | SIC424CD-T1-GE3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 44MLP-28 |
| 标准包装： | 1 |
| 系列： | microBUCK® |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.75 V ~ 5.5 V |
| 输入电压： | 3 V ~ 28 V |
| 频率 - 开关： | 200kHz ~ 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 28-MLPQ（4x4） |
| 其它名称： | SIC424CD-T1-GE3DKR |
SiC414, SiC424
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Symbol
V IN = 12 V, V5V = 5 V, T A = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
Min.
Typ.
Max.
Unit
T J = < 125 °C
Power Good
Power Good Threshold Voltage
Start-Up Delay Time
(between PWM enable and P GOOD high)
Fault (noise-immunity) Delay Time b
Power Good Leakage Current
Power Good On-Resistance
PG_V TH_UPPER
PG_T d
PG_I CC
PG_I LK
PG_R DS-ON
Upper limit, V FB > internal reference 750 mV
Lower limit, V FB < internal reference 750 mV
V5V = 5 V
V5V = 3 V
+ 20
- 10
4
2
5
10
1
%
ms
μs
μA
?
Fault Protection
Valley Current Limit
I LIM Source Current
I LIM
V5V = 5 V, R ILIM = 5 k ?
3
4
8
5
A
μA
I LIM Comparator Offset Voltage
V ILM-LK
With respect to A GND
-8
0
+8
mV
Output Under-Voltage Fault
V OUV_Fault
V FB with respect to Internal 750 mV
reference, 8 consecutive clocks
- 25
Smart Power-Save Protection
Threshold Voltage b
Over-Voltage Protection Threshold
P SAVE_VTH
V FB with respect to internal 750 mV
reference
V FB with respect to internal 750 mV
reference
+ 10
+ 20
%
Over-Voltage Fault
Delay b
t OV-Delay
5
μs
Over Temperature Shutdown b
T Shut
10 °C hysteresis
150
°C
Logic Inputs/Outputs
Logic Input High Voltage
Logic Input Low Voltage
EN/PSV
Input for PSAVE Operation b
EN/PSV
Input for Forced Continuous Operation b
EN/PSV Input for Disabling Switcher
EN/PSV Input Bias Current
ENL Input Bias Current
FB Input Bias Current
V IH
V IL
I EN
FBL_I LK
ENL
% of V5V
EN/PSV = V5V or A GND
V IN = 28 V
FB = V5V or A GND
1
45
1V
0
- 10
-1
11
0.4
100
42
0.4
+ 10
18
+1
V
%
V
μA
Linear Dropout Regulator
V LDO Accuracy
LDO Current Limit
V LDO_ACC
LDO_I LIM
V LDO load = 10 mA
Start-up and foldback, V IN = 12 V
Operating current limit, V IN = 12 V
4.9
135
5
115
200
5.1
V
mA
V LDO to V OUT Switch-Over Threshold
c
V LDO to V OUT Non-Switch-Over Threshold c
V LDO to V OUT Switch-Over Resistance
LDO Drop Out Voltage d
V LDO-BPS
V LDO-NBPS
R LDO
V OUT = 5 V
From V IN to V VLDO , V VLDO = 5 V,
I VLDO = 100 mA
- 140
- 450
2
1.2
+ 140
+ 450
mV
?
V
Notes:
a. V IN UVLO is programmable using a resistor divider from V IN to ENL to A GND . The ENL voltage is compared to an internal reference.
b. Guaranteed by design.
c. The switch-over threshold is the maximum voltage differential between the V LDO and V OUT pins which ensures that V LDO will internally
switch-over to V OUT . The non-switch-over threshold is the minimum voltage differential between the V LDO and V OUT pins which ensures that
V LDO will not switch-over to V OUT .
d. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
Document Number: 63388
S13-0248-Rev. B, 04-Feb-13
For technical questions, contact: powerictechsupport@vishay.com
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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