
Advanced Notebook I/O for ISA or LPC Designs
Datasheet
SMSC SIO10N268
Page 119
Rev. 0.5 (03-24-05)
DATASHEET
6) The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the
termination phase of the cycle.
7) The chip drives the final sync and deasserts nDATASTB or nADDRSTRB.
8) Peripheral tri-states the PData bus.
9) Chip may modify nWRITE, PDIR and nPDATA in preparation of the next cycle.
Table 8.41 - EPP Pin Descriptions
EPP
SIGNAL
EPP NAME
TYPE
EPP DESCRIPTION
nWRITE
nWrite
O
This signal is active low. It denotes a write operation.
PD<0:7>
Address/Data
I/O
Bi-directional EPP byte wide address and data bus.
INTR
Interrupt
I
This signal is active high and positive edge triggered. (Pass
through with no inversion, Same as SPP).
WAIT
nWait
I
This signal is active low.
It is driven inactive as a positive
acknowledgement from the device that the transfer of data is
completed. It is driven active as an indication that the device is
ready for the next transfer.
DATASTB
nData Strobe
O
This signal is active low. It is used to denote data read or write
operation.
RESET
nReset
O
This signal is active low. When driven active, the EPP device
is reset to its initial operational mode.
ADDRSTB
nAddress
Strobe
O
This signal is active low. It is used to denote address read or
write operation.
PE
Paper End
I
Same as SPP mode.
SLCT
Printer Selected
Status
I
Same as SPP mode.
nERR
Error
I
Same as SPP mode.
Note 8.28
SPP and EPP can use 1 common register.
Note 8.29
nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct
EPP read cycles, PCD is required to be a low.
8.10.4 Extended Capabilities Parallel Port
ECP provides a number of advantages, some of which are listed below. The individual features are
explained in greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1) Channel addressing for low-cost
peripherals Maintains link and data layer separation Permits the use of active output drivers permits the
use of adaptive signal timing Peer-to-peer capability.