参数资料
型号: SIZ710DT-T1-GE3
厂商: Vishay Siliconix
文件页数: 2/14页
文件大小: 0K
描述: MOSFET N-CH D-S 20V POWERPAIR
标准包装: 1
系列: TrenchFET®
FET 型: 2 N 沟道(双)共漏
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 20V
电流 - 连续漏极(Id) @ 25° C: 16A,35A
开态Rds(最大)@ Id, Vgs @ 25° C: 6.8 毫欧 @ 19A,10V
Id 时的 Vgs(th)(最大): 2.2V @ 250µA
闸电荷(Qg) @ Vgs: 18nC @ 10V
输入电容 (Ciss) @ Vds: 820pF @ 10V
功率 - 最大: 27W,48W
安装类型: 表面贴装
封装/外壳: 6-PowerPair?
供应商设备封装: 6-PowerPair?
包装: 标准包装
其它名称: SIZ710DT-T1-GE3DKR
SiZ710DT
Vishay Siliconix
SPECIFICATIONS (T J = 25 °C, unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
V DS Temperature Coefficient
V GS(th) Temperature Coefficient
V DS
? V DS /T J
? V GS(th) /T J
V GS = 0 V, I D = 250 μA
V GS = 0 V, I D = 250 μA
I D = 250 μA
I D = 250 μA
I D = 250 μA
I D = 250 μA
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
20
20
19
20
- 4.8
- 5.3
V
mV/°C
Gate Threshold Voltage
Gate Source Leakage
V GS(th)
I GSS
V DS = V GS , I D = 250 μA
V DS = V GS , I D = 250 μA
V DS = 0 V, V GS = ± 20 V
Ch-1
Ch-2
Ch-1
Ch-2
1
1
2.2
2.2
± 100
± 100
V
nA
V DS = 20 V, V GS = 0 V
Ch-1
1
Zero Gate Voltage Drain Current
I DSS
V DS = 20 V, V GS = 0 V
V DS = 20 V, V GS = 0 V, T J = 55 °C
Ch-2
Ch-1
1
5
μA
V DS = 20 V, V GS = 0 V, T J = 55 °C
Ch-2
5
On-State Drain Current b
I D(on)
V DS ?? 5 V, V GS = 10 V
V DS ?? 5 V, V GS = 10 V
Ch-1
Ch-2
15
20
A
V GS = 10 V, I D = 19 A
Ch-1
0.0055 0.0068
Drain-Source On-State Resistance b
R DS(on)
V GS = 10 V, I D = 20 A
V GS = 4.5 V, I D = 16.5 A
Ch-2
Ch-1
0.0027 0.0033
0.0072 0.0090
?
V GS = 4.5 V, I D = 20 A
Ch-2
0.0034 0.0043
Forward Transconductance b
g fs
V DS = 10 V, I D = 19 A
V DS = 10 V, I D = 20 A
Ch-1
Ch-2
45
85
S
Dynamic a
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
C iss
C oss
C rss
Q g
Channel-1
V DS = 10 V, V GS = 0 V, f = 1 MHz
Channel-2
V DS = 10 V, V GS = 0 V, f = 1 MHz
V DS = 10 V, V GS = 10 V, I D = 19 A
V DS = 10 V, V GS = 10 V, I D = 20 A
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
Ch-1
820
2310
290
730
115
305
11.5
38
6.9
18
60
11
pF
Gate-Source Charge
Gate-Drain Charge
Q gs
Q gd
Channel-1
V DS = 10 V, V GS = 4.5 V, I D = 16.8 A
Channel-2
V DS = 10 V, V GS = 4.5 V, I D = 20 A
Ch-2
Ch-1
Ch-2
Ch-1
Ch-2
18.2
2.4
6.6
1.7
4.8
28
nC
Gate Resistance
R g
f = 1 MHz
Ch-1
Ch-2
0.3
0.2
1.3
0.8
2.6
1.6
?
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ? 300 μs, duty cycle ? 2 %.
www.vishay.com
2
Document Number: 65733
S11-2379-Rev. B, 28-Nov-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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