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| 型号： | SM1212E433 |
| 厂商： | Semtech |
| 文件页数： | 31/77页 |
| 文件大小： | 0K |
| 描述： | RF EVAL FOR SX1212 433MHZ ISM |
| 标准包装： | 1 |
| 类型： | 收发器，ISM |
| 频率： | 433MHz |
| 适用于相关产品： | SX1212E |
| 已供物品： | 模块，天线，电源，软件 |
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SX1212
ADVANCED COMMUNICATIONS & SENSING
3.4.10.3. Alternative OOK Demodulator Threshold Modes
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold
detectors:
Fixed threshold: The value is selected through the MCParam_OOK_floor_thresh register (refer to section
3.4.10.1 for further information concerning optimization of the floor threshold).
Average threshold: Data supplied by the RSSI block is averaged with the following cutoff frequency:
RXParam _ OOK _ cutoff = 00 ? Fcutoff =
BR
8 * π
RXParam _ OOK _ cutoff = 11 ? Fcutoff =
BR
32 * π
In the first example, the higher cut-off frequency enables a sequence of up to 8 consecutive “0” or “1” to be
supported, whilst the lower cut-off frequency presented in the second example allows for the correct reception of up
to 32 consecutive “0” or “1”.
3.4.11. Bit Synchronizer
The Bit Synchronizer (BitSync) is a block that provides a clean and synchronized digital output, free of glitches.
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output
To pin DATA and
DCLK in continuous
mode
DCLK
IRQ_1
Figure 24: BitSync Description
The BitSync can be disabled through the bits RXParam_Bitsync_off, and by holding pin IRQ1 low. However, for
optimum receiver performance, its use when running Continuous mode is strongly advised. With this option a
DCLK signal is present on pin IRQ_1.
The BitSync is automatically activated in Buffered and Packet modes. The bit synchronizer bit-rate is controlled by
MCParam_BR. For a given bit rate, this parameter is determined by:
BR =
F XTAL
64 * [ 1 + MCParam _ BR ]
Rev 2 – June 18th, 2009
Page 31 of 77
www.semtech.com
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