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参数资料
| 型号： | SM320C6201BGLPW20 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封装： | CERAMIC, MO-156, BGA-429 |
| 文件页数： | 19/66页 |
| 文件大小： | 971K |
| 代理商： | SM320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
clock PLL
All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives
the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. For
the C6201B, it must be powered by the I/O voltage (3.3 V).
To configure the C62x PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter, a
single clean power supply should power both the C62x device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input
clock timing requirements. Guidelines for EMI filter selection are as follows: maximum attenuation frequency
= 20-30 MHz, maximum dB attenuation = 45-50 db, and minimum dB attenuation above 30 MHz = 20 dB.
CLKIN
PLLV
PLLF
PLLG
010 – C6201B CLKOUT1 Frequency Range 130–233 MHz
001 – C6201B CLKOUT1 Frequency Range 65–200 MHz
000 – C6201B CLKOUT1 Frequency Range 50–140 MHz
PLLFREQ3
PLLFREQ2
PLLFREQ1
CLKOUT
11
01
10
00
– MULT
×4
– Reserved
– MULT
×1
f(CLKOUT)=f(CLKIN)
×4
f(CLKOUT)=f(CLKIN)
10
F
0.1
F
(Bypass)
C1
C2
R1
3.3 V
CLKMODE0
CLKMODE1
CLKOUT1
CLKOUT2
SSCLK
SDCLK
EMIF
C6201B
2.5 V
GND
2
1 IN
3 OUT
EMI
Filter
NOTES: A. For the C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used for the C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b for the
C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved.
D. For the C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage,
DVDD.
Figure 6. PLL Block Diagram
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相关代理商/技术参数 |
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|---|---|
| SM320C6201BS14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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