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参数资料
| 型号： | SM320C6201BGLPW20 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封装： | CERAMIC, MO-156, BGA-429 |
| 文件页数： | 42/66页 |
| 文件大小： | 971K |
| 代理商： | SM320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
EXTERNAL INTERRUPT TIMING
timing requirements for interrupt response cycles (see Figure 27)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
2
tw(ILOW)
Width of the interrupt pulse low
*2P
ns
3
tw(IHIGH)
Width of the interrupt pulse high
*2P
ns
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
*Not production tested.
switching characteristics during interrupt response cycles§ (see Figure 27)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tR(EINTH-IACKH)
Response time, EXT_INTx high to IACK high
*9P
ns
4
td(CKO2L-IACKV)
Delay time, CLKOUT2 low to IACK valid
*–4
6
ns
5
td(CKO2L-INUMV)
Delay time, CLKOUT2 low to INUMx valid
6
ns
6
td(CKO2L-INUMIV) Delay time, CLKOUT2 low to INUMx invalid
*–4
ns
§ P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2
× CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
*Not production tested.
Interrupt Number
6
5
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
Figure 27. Interrupt Timing
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相关代理商/技术参数 |
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| SM320C6201BS14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
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