![](http://datasheet.mmic.net.cn/140000/SMJ320C6201BGLPW20_datasheet_5012293/SMJ320C6201BGLPW20_36.png)
SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
36
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)
NO
C6201B
UNIT
NO.
MIN
MAX
UNIT
7
tsu(EDV-SSCLKH)
Setup time, read EDx valid before SSCLK high
1.7
ns
8
th(SSCLKH-EDV)
Hold time, read EDx valid after SSCLK high
1.5
ns
switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 15 and Figure 16)
NO
PARAMETER
C6201B
UNIT
NO.
PARAMETER
MIN
MAX
UNIT
1
tosu(CEV-SSCLKH)
Output setup time, CEx valid before SSCLK high
0.5P – 1.3
ns
2
toh(SSCLKH-CEV)
Output hold time, CEx valid after SSCLK high
0.5P – 2.3
ns
3
tosu(BEV-SSCLKH)
Output setup time, BEx valid before SSCLK high
0.5P – 1.3
ns
4
toh(SSCLKH-BEIV)
Output hold time, BEx invalid after SSCLK high
*0.5P – 2.3
ns
5
tosu(EAV-SSCLKH)
Output setup time, EAx valid before SSCLK high
0.5P – 1.3
ns
6
toh(SSCLKH-EAIV)
Output hold time, EAx invalid after SSCLK high
*0.5P – 2.3
ns
9
tosu(ADSV-SSCLKH)
Output setup time, SSADS valid before SSCLK high
0.5P – 1.3
ns
10
toh(SSCLKH-ADSV)
Output hold time, SSADS valid after SSCLK high
0.5P – 2.3
ns
11
tosu(OEV-SSCLKH)
Output setup time, SSOE valid before SSCLK high
0.5P – 1.3
ns
12
toh(SSCLKH-OEV)
Output hold time, SSOE valid after SSCLK high
0.5P – 2.3
ns
13
tosu(EDV-SSCLKH)
Output setup time, EDx valid before SSCLK high
0.5P – 1.3
ns
14
toh(SSCLKH-EDIV)
Output hold time, EDx invalid after SSCLK high
*0.5P – 2.3
ns
15
tosu(WEV-SSCLKH)
Output setup time, SSWE valid before SSCLK high
0.5P – 1.3
ns
16
toh(SSCLKH-WEV)
Output hold time, SSWE valid after SSCLK high
0.5P – 2.3
ns
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
*Not production tested.