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参数资料
| 型号： | SM320C6201BGLPW20 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 200 MHz, OTHER DSP, CBGA429 |
| 封装： | CERAMIC, MO-156, BGA-429 |
| 文件页数： | 66/66页 |
| 文件大小： | 971K |
| 代理商： | SM320C6201BGLPW20 |
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B – APRIL 2000 – REVISED AUGUST 2001
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
A14
I
Clock Input
CLKOUT1
Y6
O
Clock output at full device speed
CLKOUT2
V9
O
Clock output at half of device speed
CLKMODE1
B17
I
Clock mode select
CLKMODE0
C17
I
Selects whether the output clock frequency = input clock freq x4 or x1
PLLFREQ3
C13
PLL frequency range (3, 2, and 1)
PLLFREQ2
G11
I
The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.
PLLFREQ1
F11
I
PLLV
D12
A§
PLL analog VCC connection for the low-pass filter
PLLG
G10
A§
PLL analog GND connection for the low-pass filter
PLLF
C12
A§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
K19
I
JTAG test port mode select (features an internal pull-up)
TDO
R12
O/Z
JTAG test port data out
TDI
R13
I
JTAG test port data in (features an internal pull-up)
TCK
M20
I
JTAG test port clock
TRST
N18
I
JTAG test port reset (features an internal pull-down)
EMU1
R20
I/O/Z
Emulation pin 1, pull-up with a dedicated 20-k
resistor
EMU0
T18
I/O/Z
Emulation pin 0, pull-up with a dedicated 20-k
resistor
RESET AND INTERRUPTS
RESET
J20
I
Device reset
NMI
K21
I
Nonmaskable interrupt
Edge-driven (rising edge)
EXT_INT7
R16
EXT_INT6
P20
I
External interrupts
EXT_INT5
R15
I
External interru ts
Edge-driven (rising edge)
EXT_INT4
R18
gg
g
IACK
R11
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
T19
INUM2
T20
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1
T14
O
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt service fetch packet ordering
INUM0
T16
Encoding order follows the interru t service fetch acket ordering
LITTLE ENDIAN/BIG ENDIAN
LENDIAN
G20
I
If high, selects little-endian byte/half-word addressing order within a word
If low, selects big-endian addressing
POWER DOWN STATUS
PD
D19
O
Power-down mode 2 or 3 (active if high)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect
those pins.
§ A = Analog Signal (PLL Filter)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320C6201BS14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6201BS16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6201BW14 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6201BW16 | 制造商:TI 制造商全称:Texas Instruments 功能描述:FLOATING-POINT DIGITAL SIGNAL PROCESSOR |
| SM320C6201-EP | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
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