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参数资料
| 型号： | SM320VC33HFGM150 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 75 MHz, OTHER DSP, CQFP164 |
| 封装： | NCTB, CERAMIC, MO-113AA, QFP-164 |
| 文件页数： | 7/56页 |
| 文件大小： | 669K |
| 代理商： | SM320VC33HFGM150 |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
EDGEMODE
When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the
interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer
than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the
logic-low and logic-high states is sufficient.
When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU
or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied
if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine
(ISR), effectively lengthening the maximum ISR width.
After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload
operation.
CPU Set
IF Bit
RESET
EDGEMODE
CPU Reset
INTn
H1
Delay
DD Q
Q
R
S
DQ
H3
Figure 7. EDGEMODE and Interrupt Flag CIrcuit
reset operation
When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in
progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in
an inactive or high-impedance state.
When both RESET and SHZ are applied, the device will immediately enter the reset state with the pins held in
high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ
can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system
conflicts.
PAGE0 - PAGE3 select lines
To facilitate simpler and higher speed connection to external devices, the SM/SMJ320VC33 includes four
predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB
and are active only during external accesses over the ranges shown in Table 4. All external bus accesses are
controlled by a single bus control register.
Table 4. PAGE0 - PAGE3 Ranges
START
END
PAGE0
0x000000
0x3FFFFF
PAGE1
0x400000
0x7FFFFF
PAGE2
0x800000
0xBFFFFF
PAGE3
0xC00000
0xFFFFFF
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SM320VC33PGEA120EP | 功能描述:数字信号处理器和控制器 - DSP, DSC EP Dig Signal Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| SM320VC5409-EP | 制造商:TI 制造商全称:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| SM320VC5409GGU10EP | 功能描述:数字信号处理器和控制器 - DSP, DSC Fxd-pt Dig Sig Proc Mil enhanced RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| SM320VC5416-EP | 制造商:TI 制造商全称:Texas Instruments 功能描述:SM320VC5416-EP Fixed-Point Digital Signal Processor |
| SM320VC5416GGU16EP | 功能描述:数字信号处理器和控制器 - DSP, DSC Fxd-pt Dig Sig Proc Mil enhanced RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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