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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
local memory and DRAM/VRAM interface (continued)
Similarly, for each of the other VRAM modes, direct connection is provided for other DRAM modes requiring
larger matrices than the configuration mode. Table 4 gives examples of the connections using this feature.
Table 4. Connections to RCA for CAMD = 1
RCA
64K
256K
1M
4M
12
1M × 32
4M × 32
16M × 32
11
1M × 16
1M × 32
4M × 32
4M × NN
16M × 32
10
256K × 32
1M × 32
1M × NN
4M × 32
4M × NN
16M × 32
9
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
8
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
7
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
6
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
5
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
4
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
3
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
2
256K × NN
1M × NN
4M × 32
4M × NN
16M × 32
1
256K × 16
1M × 16
4M × 16
0
16M × 32
NN is used for either 16-bit (× 16) or 32-bit (× 32) memory connections.
status codes
Status codes are output on LAD0--LAD3 at the time of the falling edge of ALTCH and can be used to determine
the type of cycle that is being initiated. Table 5 lists the codes and their respective meanings.
Table 5. Status Codes Output on LAD0--LAD3
CODE
STATUS
TYPE
0000
Coprocessor code
0001
Emulator operation
OTHER
0010
Host cycle
(00XX)
0011
DRAM refresh
0100
Video-generated DRAM serial register transfer
0101
CPU-generated VRAM serial register transfer
VRAM
0110
Write mask load
(01XX)
0111
Color latch load
1000
Data access
1001
Cache fill
1010
Instruction fetch
1011
Interrupt vector fetch
CPU
1100
Bus locked operation
(1XXX)
1101
Pixel operation
1110
Block write
1111
-- RESERVED --