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| 型号： | SM34020AHTM32 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 图形处理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封装： | CERAMIC, QFP-132 |
| 文件页数： | 15/98页 |
| 文件大小： | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
22
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
clock stretch (continued)
The clock-stretch mechanism allows the SMJ34020A to slow down and execute those critical local-memory
cycles while still benefiting from the accelerated processing allowed by higher CLKIN frequencies during
noncritical memory access cycles.
Exact timing issues vary from system to system, reflecting differences in bus buffering, etc., but, broadly
speaking, the clock-stretch mechanism allows the system designer to interface to slower memory devices than
the designer could use if no stretch mechanism was available.
A normal, unstretched machine cycle consists of four quarter cycles, Q1, Q2, Q3, and Q4. A stretched cycle
consists of five quarter cycles, Q1, Q2, Q3, Q4a, and Q4b.
When clock-stretch mode is enabled, the fourth machine quarter cycle can be stretched to twice its original
length. See Figure 3 for an example. This stretching takes place only when the SMJ34020A attempts certain
types of memory cycles.
Q4
Q3
Q2
Q1
Q4b
Q4a
Q3
Q2
Q1
Stretched Cycle
Normal Cycle
Q4
Q3
Q2
Q1
Q4
Q3
Q2
Q1
Normal Sequence
Possible New Sequence
Figure 3. Stretched Machine Quarter Cycle
The stretch is achieved by holding the internal SMJ34020A clocks in the Q4 state for an extra quarter cycle so
all of the device outputs remain unchanged during Q4a and Q4b. The SMJ34020A stretches only certain
machine cycles so that the execution of code is not slowed unnecessarily.
enabling clock stretch
Clock-stretch mode is enabled and disabled using a bit in the CONFIG register memory mapped to location
C00001A0h, see Figure 4.
0
1
2
3
4
5
6
7
C
S
E
Loaded at Reset from Reset Vector
Protected Byte
CONFIG register
CSE = 0: Disable stretch mode (normal operation)
CSE = 1: Enable stretch mode
31
Figure 4. Stretch Mode Enable
Bit 4 of the CONFIG register is the clock-stretch-enable mode bit. A zero in this bit disables stretch mode and
a one in this bit enables stretch mode. The bit is cleared during reset; that is, stretch mode is disabled by default.
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