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参数资料
| 型号： | SM34020AHTM32 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 图形处理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封装： | CERAMIC, QFP-132 |
| 文件页数： | 17/98页 |
| 文件大小： | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
enabling clock stretch (continued)
READ
ADDR
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
READ
ADDR
4
3
2
1
4
3
1
4
3
2
4
3
2
11
2
Stretch
Stretch Mode Enabled
Stretch Mode Disabled
Figure 7. Three 32-Bit Page-Mode Reads
The stretched cycles are designed to accommodate worst-case 32-bit page-mode accesses, so during some
nonpage-mode memory accesses stretches that are not essential can be generated. For example:
WRITE
ADDR
READ
ADDR
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
WRITE
ADDR
READ
ADDR
4
3
2
1
4
3
4
3
2
4
3
2
11
2
Stretch
Stretch Mode Enabled
Stretch Mode Disabled
1
Stretch
Figure 8. One 32-Bit Nonpage-Mode Read-Write
Stretches are inserted in read-modify-write accesses to help ease bus turn-around timings. In the above
example, the second stretch is not needed to help these timings because the read/write turn-around has the
whole of the address cycle to evaluate.
clock-stretch timing example, SMJ34020A-32 and 150-ns DRAMs
This example analyzes a memory interface timing parameter. It shows that the clock-stretch mechanism can
be used to allow the SMJ34020A-32 to avoid a timing violation when interfaced to 100-ns VRAMs.
Consider a system with:
D
A SMJ34020A-32,
which has a 32-MHz clock input frequency and hence a 125-ns cycle time, so
tQ = 31 ns. Timing parameters are taken from this data sheet.
D
A SMJ44C251-10
1 megabit × 1 bit DRAM. Timing parameters are taken from the corresponding
Texas Instruments data sheet.
row address hold data after RAS low, th(ADV-REL)
Without clock stretch
SMJ4C1024 th(RA)
Hold time, row address valid after RAS low
Min = 20 ns
SMJ34020A Parameter 88 Hold time, row address valid after RAS low
Min = tQ -- 5 ns = 26 ns
If RAS is passed through a PAL with a delay of 7 ns, then th(RA) seen by the DRAM is 26 ns -- 7 ns = 19 ns.
This violates the 20 ns minimum.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SM34020AHTM40 | 制造商:TI 制造商全称:Texas Instruments 功能描述:GRAPHICS SYSTEM PROCESSOR |
| SM34020APCM40 | 制造商:Texas Instruments 功能描述:Graphics System Processor 144-Pin PQFP 制造商:Texas Instruments 功能描述:GRAPHICS SYS PROCESSOR 144PQFP - Trays |
| SM34020GMB30 | 制造商:Texas Instruments 功能描述: |
| SM34061A WAF | 制造商:Texas Instruments 功能描述: |
| SM34061GB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Non-VGA Video Controller |
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