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参数资料
| 型号： | SM34020AHTM32 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | 图形处理器 |
| 英文描述： | GRAPHICS PROCESSOR, CQFP132 |
| 封装： | CERAMIC, QFP-132 |
| 文件页数： | 9/98页 |
| 文件大小： | 1546K |
| 代理商： | SM34020AHTM32 |
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SMJ34020A
GRAPHICS SYSTEM PROCESSOR
SGUS011D -- APRIL 1991 -- REVISED SEPTEMBER 2004
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
local memory and DRAM/VRAM interface (continued)
Table 2. Basic Memory Row/Column Access Modes
RCM1
RCM
VRAM
MODE
ADDRS
BANKS§
CAMD SUPPORT MATRICES
0
64K × N
8
16
64K × 16, 64K × 32, 256K × 16, 256K × 32, 1M × 16, 1M × 32
0
1
256K × N
9
8
2564K × 16, 256K × 32, 1M × 16, 1M × 32, 4M × 32
1
0
1M × N
10
4
1M × 16, 1M × 32, 4M × 16, 4M × 32
1
4M × N
11
2
4M × 16, 4M × 32, 16M × 32
VRAM mode = basic size of VRAM addressing supported with CAMD = 0
Addrs = number of RCA signals required to provide row/column addressing
§ Banks = number of possible interleaved 32-bit wide memory spaces
CAMD support = possible sizes and configurations of DRAMs that can be supported within the basic VRAM mode
Table 3 lists the actual logical address bits output on each of the RCA lines during row and column intervals for
each of the four VRAM modes and states of CAMD.
Table 3. Logical Address Bit Output
ROW TIME
COLUMN TIME
CAMD = 0
CAMD = 1
RCA BIT
64K
256K
1M
4M
64K
256K
1M
4M
12
24
25
26
27
16
23
26
15
28
11
23
24
25
26
15
22
14
10
22
23
24
25
14
13
9
21
22
23
24
13
12
8
20
21
22
23
12
11
7
19
20
21
22
11
10
6
18
19
20
21
10
9
99
9
5
17
18
19
20
9
8
88
8
4
16
17
18
19
8
7
77
7
3
15
16
17
18
7
6
66
6
2
14
15
16
17
6
5
55
5
1
13
14
15
16
5
4
44
4
0
12
13
14
15
4
16
In the 64K mode with CAMD=0, any eight adjacent RCA0--RCA12 pins output 16 contiguous logical address
bits. The eight most significant addresses are output during row-address time while the least significant
addresses are output during column-address time. Logical addresses 12 through 16 are output twice during a
memory cycle (during both RAS and CAS falling edges) but at different pins. This allows a variety of VRAM
memory organizations and decoding schemes to be used. When CAMD = 1, the addresses output during
column-address time are changed such that a new logical address mapping occurs, allowing connection of RCA
directly to 256K or 1M DRAMs.
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