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参数资料
型号： SN65LVDS305ZQE
厂商： Texas Instruments, Inc.
英文描述： PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
中文描述： 可编程27位显示器串行接口变送器
文件页数： 10/25页
文件大小： 586K
代理商： SN65LVDS305ZQE
www.ti.com
DISSIPATION RATINGS
THERMAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
(1)
SN65LVDS305
SLLS744–AUGUST 2006
CIRCUIT
BOARD MODEL
Low-K
(2)
DERATING FACTOR
(1)
ABOVE T
A
= 25
°
C
7.407 mW/
°
C
T
= 85
°
C
POWER RATING
148 mW
PACKAGE
T
A
< 25
°
C
ZQE
592 mW
(1)
(2)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the low-K thermal metric definitions of EIA/JESD51-2.
PARAMETER
TEST CONDITIONS
VALUE
22.3
36.7
UNIT
PCLK at 4 MHz
PCLK = 15 MHz
P
D
Device power dissipation, maximum
V
DDx
= 1.95 V, T
A
= –40
°
C
mW
MIN
NOM
MAX
UNIT
V
DD
V
DDPLLA
V
DDPLLD
V
DDLVDS
Supply voltages
1.65
1.8
1.95
V
Supply voltage noise
magnitude 50 MHz (all
supplies)
Test setup see
Figure 10
f(noise) = 1Hz to 2
GHz
V
DDn(PP)
100
mV
1-channel transmit mode, see
Figure 3
Frequency threshold Standby mode to active
mode
(2)
, see
Figure 14
4
15
f
PCLK
Pixel clock frequency
MHz
0.5
3
t
H
x f
PCLK
PCLK input duty cycle
Operating free-air
temperature
PCLK RMS period jitter
(3)
PCLK total jitter
PCLK peak
cycle-to-cycle jitter
(4)
0.33
0.67
T
A
–40
85
°
C
t
jit(per)PCLK
t
jit(TJ)PCLK
5
ps-rms
s
0.05/f
PCLK
Measured on PCLK input
t
jit(CC)PCLK
0.02/f
PCLK
s
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, CPOL, TXEN, SWAP
V
IH
High-level input voltage
V
IL
Low-level input voltage
Data set up time prior to
t
DS
PCLK transition
Data hold time after PCLK
t
DH
transition
0.7 V
DD
V
DD
V
V
0.3 V
DD
f (PCLK) = 10 MHz; see
Figure 6
2
ns
2
ns
(1)
(2)
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS305 into standby mode. Input frequencies between 500 kHz and
3 MHz may or may not activate the SN65LVDS305. Input frequencies beyond 3 MHz activate the SN65LVDS305.
Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles over a random sample of 1,000 adjacent cycle
pairs.
(3)
(4)
10
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SN65LVDS306ZQER 功能描述:串行器/解串器 - Serdes QVGAVGA 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64
SN65LVDS307ZQCR 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64
SN65LVDS307ZQCT 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64
SN65LVDS308ZQCR 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64
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