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参数资料
| 型号： | SN65LVDS305ZQE |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER |
| 中文描述： | 可编程27位显示器串行接口变送器 |
| 文件页数： | 7/25页 |
| 文件大小： | 586K |
| 代理商： | SN65LVDS305ZQE |
www.ti.com
FUNCTIONAL DESCRIPTION
D+/– CHANNEL
CLK+
B7 B6
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
B5 B4 B3 B2 B1 B0 VS HS DE 0
0 CP R7 R6
CP
0
0
CLK–
Power-Down Modes
The SN65LVDS305 transmitter has two power-down modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS305 enters shutdown mode when the TXEN terminal is asserted low. This turns off all
transmitter circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All
outputs are high-impedance. Current consumption in shutdown mode is nearly zero.
Standby Mode
The SN65LVDS305 enters the standby mode if TXEN is high and the PCLK input signal frequency is less than
500 kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter the high-impedance
state. The current consumption in standby mode is very low. When the PCLK input signal is completely stopped,
the I
DD
current consumption is less than 10
μ
A. The PCLK input must not be left floating.
Active Modes
When TXEN is high and the PCLK input clock signal is faster than 3 MHz, the SN65LVDS305 enters the active
mode. Current consumption in the active mode depends on operating frequency and the number of data
transitions in the data payload.
Acquire Mode (PLL Approaches Lock)
The PLL is enabled and attempts to lock to the input clock. All outputs remain in the high-impedance state.
When the PLL monitor detects stable PLL operation, the device switches from the acquire mode to the transmit
mode. For proper device operation, the pixel clock frequency must fall within the valid f
range specified
under recommended operating conditions. If the pixel clock frequency is larger than 3MHz but smaller than
f
PCLK
(min), the SN65LVDS305 PLL is enabled. Under such conditions, it is possible for the PLL to lock
temporarily to the pixel clock, causing the PLL monitor to release the device into transmit mode. If this happens,
the PLL may or may not be properly locked to the pixel clock input, potentially causing data errors, frequency
oscillation, and PLL deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK terminal outputs a copy of
PCLK.
SN65LVDS305
SLLS744–AUGUST 2006
The SN65LVDS305 transmits payload data over a single SubLVDS data pair, D. The PLL locks to PCLK and
internally multiplies the clock by a factor of 30. The internal high-speed clock is used to serialize (shift out) the
data payload on D. Two reserved bits and the parity bit are added to the data frame.
Figure 3
illustrates the
timing and the mapping of the data payload into the 30-bit frame. The internal high-speed clock is divided by a
factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output. While in this mode, the PLL
can lock to a clock that is in the range of 4 MHz through 15 MHz. This is intended for smaller video display
formats (e.g. QVGA to HVGA) .
Figure 3. Data and Clock Output
NOTE:
A floating (left open) CMOS input allows leakage currents to flow from V
DD
to GND.
To prevent large leakage current, a CMOS gate must be kept at a valid logic level,
either V
or V
. This can be achieved by applying an external voltage of V
IH
or V
IL
to
all SN65LVDS305 inputs.
7
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SN65LVDS305ZQER | 功能描述:串行器/解串器 - Serdes QVGAVGA 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS306ZQER | 功能描述:串行器/解串器 - Serdes QVGAVGA 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS307ZQCR | 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS307ZQCT | 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS308ZQCR | 功能描述:串行器/解串器 - Serdes 27B Display Ser Interface Trnsmitter RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
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