参数资料
型号: SNJ54LVT8986HV
厂商: Texas Instruments, Inc.
英文描述: 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
中文描述: 3.3 V的连接寻址扫描港口多点寻址IEEE标准1149.1(JTAG接口)技术咨询收发器
文件页数: 21/51页
文件大小: 880K
代理商: SNJ54LVT8986HV
SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
OCTOBER 2002
REVISED APRIL 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Update-IR
The LASP is not enabled to receive and respond to linking shadow protocols in the Update-IR state. For target
devices, the current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
address matching
Connect status of the LASP is computed by a match of the address received in the last valid linking-shadow
protocol against that at the address (A
9
A
0
) inputs as well as against the three dedicated addresses that are
internal to the LASP (DSA, RSA, and TSA). Table 2 shows the address map.
Table 2. Address Map
ADDRESS
NAME
BINARY
CODE
HEX CODE
LINK SHADOW
PROTOCOL RESULT
RESULTANT
PRIMARY-TO-SECONDARY
CONNECT STATUS
Reset address (RSA)
0000000000
000
RESET
RESET
Matching address
A9
A0
1111111110
A9
A0
3FE
MATCH
ON
Disconnect address (DSA)
DISCONNECT
OFF
Test Synchronization address (TSA)
1111111111
3FF
TEST SYNCHRONIZATION
MULTICAST
All other addresses
All others
All others
NO MATCH
OFF
Upon receipt of a valid linking shadow protocol, if the linking shadow protocol address and position match the
address inputs A
9
A
0
and position inputs P
2
P
0
respectively, the LASP responds by transmitting an
acknowledge protocol. Following the complete transmission of the acknowledge protocol, the LASP assumes
ON status, in which the secondary TAPs are configured as requested by the linking shadow protocol. The ON
status allows the scan chains associated with the LASP secondary TAPs to be controlled from the multidrop
primary TAP as if it were directly wired as such. Figures 9 and 10 show the linking shadow protocol timing for
MATCH result when the prior LASP connect status is ON and OFF, respectively. If the linking-shadow protocol
address or position does not match the address inputs A
9
A
0
or position inputs P
2
P
0
(unless the address is
one of the three dedicated global addresses described below), the LASP responds immediately by assuming
the OFF status, in which PTDO and STDO
2
STDO
0
are high impedance and STMS
2
STMS
0
are held at their
last levels. This has the effect of deselecting the scan chains associated with the LASP secondary TAPs, but
leaves the TAP state of the scan chains unchanged. No acknowledge protocol is sent. Figures 11 and 12 show
the linking shadow protocol timing for a NO MATCH result when the prior LASP connect status is ON and OFF,
respectively.
disconnect address
The disconnect address (DSA) is one of the three internally dedicated addresses that are recognized globally.
When an LASP receives the DSA, it immediately responds by assuming the OFF status, in which PTDO and
STDO
2
STDO
0
are high impedance and STMS
2
STMS
0
are held at their last levels. This has the effect of
deselecting the scan chain associated with the LASP secondary TAP, but leaves the TAP state of the scan chain
unchanged. No acknowledge protocol is sent. Figures 13 and 14 show the linking shadow protocol timing for
DISCONNECT result when the prior LASP connect status is ON and OFF, respectively. The same result occurs
when a nonmatching address is received. No specific action to disconnect an LASP is required, as a given LASP
is disconnected by the address that connects another. The dedicated DSA ensures that at least one address
is available for the purpose of disconnecting all receiving LASPs. It is especially useful when the currently
selected scan chain is in a different TAP state than that to be selected. In such a case, the DSA is used to leave
the former scan chain in the proper state, after which the primary TAP state is moved to that needed to select
the latter scan chain.
相关PDF资料
PDF描述
SNJ54LVTH241W 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54LVTH241 Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000
SN54LVTH241FK Octal 3-State Non-Inverting Transparent Latch; Package: SOIC-20 WB; No of Pins: 20; Container: Tape and Reel; Qty per Container: 1000
SN54LVTH241J Octal 3-State Non-Inverting Transparent Latch; Package: SOEIAJ-20; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2000
SNJ54LVTH241FK 3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
相关代理商/技术参数
参数描述
SNJ54LVTH162244WD 制造商:Texas Instruments 功能描述:Buffer/Line Driver 16-CH Non-Inverting 3-ST BiCMOS 48-Pin CFPAK Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk
SNJ54LVTH162245WD 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:TISSNJ54LVTH162245WD 3.3-V ABT 16BIT BUS 制造商:Texas Instruments 功能描述:Bus XCVR Dual 16-CH 3-ST 48-Pin CFPAK Tube
SNJ54LVTH162373WD 制造商:Texas Instruments 功能描述:TISSNJ54LVTH162373WD 5962-9763801QXA
SNJ54LVTH162374WD 制造商:Texas Instruments 功能描述:
SNJ54LVTH16244AWD 制造商:Texas Instruments 功能描述:Buffer/Line Driver 16-CH Non-Inverting 3-ST BiCMOS 48-Pin CFPAK Tube