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| 型号： | SNJ54LVT8986HV |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS |
| 中文描述： | 3.3 V的连接寻址扫描港口多点寻址IEEE标准1149.1（JTAG接口）技术咨询收发器 |
| 文件页数： | 4/51页 |
| 文件大小： | 880K |
| 代理商： | SNJ54LVT8986HV |
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SN54LVT8986, SN74LVT8986
3.3-V LINKING ADDRESSABLE SCAN PORTS
MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
SCBS759B
–
OCTOBER 2002
–
REVISED APRIL 2003
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54LVT8986 . . . HV PACKAGE
(TOP VIEW)
NC
–
No internal connection
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
PX
V
CC
PY
GND
CTDO
PTDO
CTDI
PTDI
NC
PTMS
PTCK
PTRST
BYP
5
BYP
4
BYP
3
BYP
2
BYP
1
STDI
1
STMS
1
STCK
1
GND
STRST
1
CON
0
SX
0
V
CC
NC
C
S
S
S
G
C
S
S
S
A
7
A
8
A
9
P
0
A
2
G
A
3
A
4
A
5
V
A
6
A
0
S
V
P
1
P
B
S
S
V
S
A
1
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
0
C
1
1
1
1
2
2
2
2
2
2
2
2
2
5
6
N
N
SY
0
STDO
0
STDI
0
GND
STMS
0
STCK
0
STRST
0
OE
C
G
description/ordering information (continued)
Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered
directly onto the secondary test clock (STCK
2
–
STCK
0
) outputs. Upon power up of the device, the LASP
assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass
signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting
the primary test reset (PTRST) input or by using the linking shadow protocol. PTRST always is buffered directly
onto the secondary test reset (STRST
2
–
STRST
0
) outputs, ensuring that the LASP and its associated secondary
TAPs can be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary
test data inputs (STDI
2
–
STDI
0
). Secondary test data outputs (STDO
2
–
STDO
0
) can be configured to receive
either the primary test data input (PTDI), STDI
2
–
STDI
0
, or the cascade test data input (CTDI). Cascade test data
output (CTDO) can be configured to receive either of STDI
2
–
STDI
0
, or CTDI. CTDI and CTDO facilitate
cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode
select (STMS
2
–
STMS
0
) outputs can be configured to receive the primary test-mode select (PTMS) input. When
any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the
secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held
in its last stable state.
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