参数资料
型号: SST25VF064C-80-4C-Q2AE-T
厂商: Microchip Technology
文件页数: 19/37页
文件大小: 0K
描述: IC FLASH SER 64M DUAL I/O 8WSON
标准包装: 2,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 64M(8M x 8)
速度: 80MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-WDFN 裸露焊盘
供应商设备封装: 8-WSON
包装: 带卷 (TR)
64 Mbit SPI Serial Dual I/O Flash
A Microchip Technology Company
SST25VF064C
Data Sheet
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the selected 32 KByte block to FFH. A Block-
Erase instruction applied to a protected memory area will be ignored. The 64-KByte Block-Erase instruc-
tion clears all bits in the selected 64 KByte block to FFH. A Block-Erase instruction applied to a protected mem-
ory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of any command sequence. The 32-KByte Block-Erase
instruction is initiated by executing an 8-bit command, 52H, followed by address bits A 23 -A 0 . Address
bits A MS -A 15 (A MS = Most Significant Address) are used to determine block address (BA X ), remaining
address bits can be V IL or V IH. CE# must be driven high before the instruction is executed. The 64-KByte Block-
Erase instruction is initiated by executing an 8-bit command D8H, followed by address bits A 23 -A 0 . Address bits
A MS -A 15 are used to determine block address (BA X ), remaining address bits can be V IL or V IH. CE# must be
driven high before the instruction is executed. Poll the Busy bit in the software status register or wait T BE for
the completion of the internal self-timed 32-KByte Block-Erase or 64-KByte Block-Erase cycles. See
Figure 13 for the 32-KByte Block-Erase sequence and Figure 14 for the 64-KByte Block-Erase
sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31
SCK
MODE 0
SI
52
ADDR
ADDR
ADDR
SO
MSB
MSB
HIGH IMPEDANCE
1392 F32.0
Figure 13: 32-KByte Block-Erase Sequence
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31
SCK
MODE 0
SI
D8
ADDR
ADDR
ADDR
SO
MSB
MSB
HIGH IMPEDANCE
1327 F33.0
Figure 14: 64-KByte Block-Erase Sequence
?2011 Silicon Storage Technology, Inc.
19
DS25036A
06/11
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