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参数资料
| 型号： | SST29LE512-150-4I-EHE |
| 厂商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分类： | PROM |
| 英文描述： | 64K X 8 FLASH 3V PROM, 150 ns, PDSO32 |
| 封装： | 8 X 20 MM, MO-142BD, TSOP1-32 |
| 文件页数： | 22/28页 |
| 文件大小： | 348K |
| 代理商： | SST29LE512-150-4I-EHE |
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Data Sheet
512 Kbit Page-Write EEPROM
SST29EE512 / SST29LE512 / SST29VE512
3
2003 Silicon Storage Technology, Inc.
S71060-08-000
11/03 301
Write Operation Status Detection
The SST29EE/LE/VE512 provide two software means to
detect the completion of a Write cycle, in order to optimize
the system Write cycle time. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle Bit
(DQ6). The end of write detection mode is enabled after the
rising WE# or CE# whichever occurs first, which initiates
the internal Write cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ7)
When the SST29EE/LE/VE512 are in the internal Write
cycle, any attempt to read DQ7 of the last byte loaded dur-
ing the byte-load cycle will receive the complement of the
true data. Once the Write cycle is completed, DQ7 will
show true data. Note that even though DQ7 may have valid
data immediately following the completion of an internal
Write operation, the remaining data outputs may still be
invalid: valid data on the entire data bus will appear in sub-
sequent successive Read cycles after an interval of 1 s.
16 for a flowchart.
Toggle Bit (DQ6)
During the internal Write cycle, any consecutive attempts to
read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling
between 0 and 1. When the Write cycle is completed, the
toggling will stop. The device is then ready for the next
operation. See Figure 8 for Toggle Bit timing diagram and
Figure 16 for a flowchart. The initial read of the Toggle Bit
will typically be a “1”.
Data Protection
The SST29EE/LE/VE512 provide both hardware and soft-
ware features to protect nonvolatile data from inadvertent
writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29EE/LE/VE512 provide the JEDEC approved
optional Software Data Protection scheme for all data alter-
ation operations, i.e., Write and Chip-Erase. With this
scheme, any Write operation requires the inclusion of a
series of three byte-load operations to precede the data
loading operation. The three-byte load sequence is used to
initiate the Write cycle, providing optimal protection from
inadvertent Write operations, e.g., during the system
power-up or power-down. The SST29EE/LE/VE512 are
shipped with the Software Data Protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
be automatically set into the data protect mode. Any
subsequent Write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ing diagrams. To set the device into the unprotected
mode, a six-byte sequence is required. See Table 4 for
the specific codes and Figure 9 for the timing diagram. If
a Write is attempted while SDP is enabled the device
will be in a non-accessible state for ~ 300 s. SST rec-
ommends Software Data Protection always be enabled.
See Figure 17 for flowcharts.
The SST29EE/LE/VE512 Software Data Protection is a
global command, protecting (or unprotecting) all pages in
the entire memory array once enabled (or disabled). There-
fore using SDP for a single Page-Write will enable SDP for
the entire array. Single pages by themselves cannot be
SDP enabled or disabled, although the page addressed
during the SDP write will be written.
Single power supply reprogrammable nonvolatile memo-
ries may be unintentionally altered. SST strongly recom-
mends that Software Data Protection (SDP) always be
enabled. The SST29EE/LE/VE512 should be programmed
using the SDP command sequence. SST recommends the
SDP Disable Command Sequence not be issued to the
device prior to writing.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST29LE512-150-4I-NH | 功能描述:闪存 64K X 8 150ns RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST29LE512-150-4I-NHE | 功能描述:闪存 64K X 8 150ns RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST29LE512-150-4I-PH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit (64K x8) Page-Mode EEPROM |
| SST29LE512-150-4I-UH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit (64K x8) Page-Mode EEPROM |
| SST29LE512-150-4I-WH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit (64K x8) Page-Mode EEPROM |
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