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参数资料
| 型号： | SST39LF040-55-4C-NHE |
| 厂商： | Microchip Technology |
| 文件页数： | 7/31页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 4MBIT 55NS 32PLCC |
| 特色产品： | SST Serial and Parallel Flash Memory |
| 标准包装： | 30 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 4M (512K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-LCC（J 形引线） |
| 供应商设备封装： | 32-PLCC |
| 包装： | 管件 |
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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
A Microchip Technology Company
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39LF010/020/040 and SST39VF010/020/040 devices are controlled by
CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE#
is the output control and is used to gate data from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure
6).
Byte-Program Operation
The SST39LF010/020/040 and SST39VF010/020/040 are programmed on a byte-by-byte basis.
Before programming, the sector where the byte exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte load sequence for Software Data Protec-
tion. The second step is to load byte address and byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed, within 20 μs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands written during the internal Pro-
gram operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse,
while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 11 for timing waveforms. Any commands written during the
Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39LF010/020/040 and SST39VF010/020/040 devices provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device
must be quickly erased.
The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command
sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal
Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the
?2011 Silicon Storage Technology, Inc.
7
DS25023A
08/11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST39LF040-55-4C-NHE-T | 功能描述:闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39LF040-55-4C-NK | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-NKE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-NME | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-WH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
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