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参数资料
| 型号： | SST39LF040-55-4C-NHE |
| 厂商： | Microchip Technology |
| 文件页数： | 9/31页 |
| 文件大小： | 0K |
| 描述： | IC FLASH MPF 4MBIT 55NS 32PLCC |
| 特色产品： | SST Serial and Parallel Flash Memory |
| 标准包装： | 30 |
| 系列： | SST39 MPF™ |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 4M (512K x 8) |
| 速度： | 55ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-LCC（J 形引线） |
| 供应商设备封装： | 32-PLCC |
| 包装： | 管件 |
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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
A Microchip Technology Company
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Data# Polling (DQ 7 )
When the SST39LF010/020/040 and SST39VF010/020/040 are in the internal Program operation, any
attempt to read DQ 7 will produce the complement of the true data. Once the Program operation is
completed, DQ 7 will produce true data. Note that even though DQ 7 may have valid data immediately
following completion of an internal Write operation, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 μs.
During internal Erase operation, any attempt to read DQ 7 will produce a “0”. Once the internal Erase
operation is completed, DQ 7 will produce a “1”. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure
18 for a flowchart.
Toggle Bit (DQ 6 )
During the internal Program or Erase operation, any consecutive attempts to read DQ 6 will produce
alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation
is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is
valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Tog-
gle Bit timing diagram and Figure 18 for a flowchart.
Data Protection
The SST39LF010/020/040 and SST39VF010/020/040 provide both hardware and software features to
protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.
V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
?2011 Silicon Storage Technology, Inc.
9
DS25023A
08/11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST39LF040-55-4C-NHE-T | 功能描述:闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST39LF040-55-4C-NK | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-NKE | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-NME | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
| SST39LF040-55-4C-WH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash |
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