- 您现在的位置：买卖IC网 > PDF目录98142 > SST89E554A-40-C-NJ (SILICON STORAGE TECHNOLOGY INC) 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 PDF资料下载
参数资料
| 型号： | SST89E554A-40-C-NJ |
| 厂商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, MS-018AC, LCC-44 |
| 文件页数： | 41/87页 |
| 文件大小： | 996K |
| 代理商： | SST89E554A-40-C-NJ |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页当前第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页
46
Preliminary Specifications
FlashFlex51 MCU
SST89E554A / SST89V554A
2003 Silicon Storage Technology, Inc.
S71228-00-000
6/03
The user could use the possible addresses above to select
slave 3 only. Another combination could be to select slave 2
and 3 only as shown below.
More than one slave may have the same SADDR address
as well, and a given address could be used to modify the
address so that it is unique.
6.1.2.2 Using the Broadcast Address to Select Slaves
Using the broadcast address, the master can communicate
with all the slaves at once. It is formed by performing a logi-
cal OR of SADDR and SADEN with ‘0’s in the result treated
as “don’t cares”.
“Don’t cares” allow for a wider range in defining the broad-
cast address, but in most cases, the broadcast address will
be FFH.
On reset, SADDR and SADEN are “0”. This produces an
given address of all “don’t cares” as well as a broadcast
address of all “don’t cares.” This effectively disables Auto-
matic Addressing mode and allows the microcontroller to
function as a standard 8051, which does not make use of
this feature.
6.2 Serial Peripheral Interface
6.2.1 SPI Features
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake up from idle mode (slave mode only)
6.2.2 SPI Description
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the SST89E/V554A and
peripheral devices or between several SST89E/V554A
devices.
Figure 6-4 shows the correspondence between master
and slave SPI devices. The SCK pin is the clock output and
input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master
devices SPI data register. The written data is then shifted
out of the MOSI pin on the master device into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be gener-
ated if the SPI Interrupt Enable bit (SPIE) and the Serial
Port Interrupt Enable bit (ES) are both set.
An external master drives the Slave Select input pin, SS#/
P1[4], low to select the SPI module as a slave. If SS#/P1[4]
has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an
input port pin.
CPHA and CPOL control the phase and polarity of the SPI
tions of these two bits.
FIGURE
6-4: SPI MASTER-SLAVE INTERCONNECTION
Select Slave 3 Only
Slave 2
Given Address
Possible Addresses
1111 X0X1
1111 1011
1111 1001
Select Slaves 2 & 3 Only
Slaves 2 & 3
Possible Addresses
1111 0011
Slave 1
1111 0001 =
SADDR
+1111 1010 =
SADEN
1111 1X11 =
Broadcast
1228 F18.0
8-bit Shift Register
MSB Master LSB
SPI
Clock Generator
MISO MISO
MOSI MOSI
SCK
SS#
8-bit Shift Register
MSB Slave LSB
VSS
VDD
相关PDF资料 |
PDF描述 |
|---|---|
| SST89E554A-40-I-TQJ | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44 |
| SSTE32882HLBAKG | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| SSTE32882HLBBKG | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| SSTUA32864EC,557 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| SSTUA32866EC/G | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SST89E554RC | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-C-NI | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-C-NJ | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-C-PI | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E554RC-25-C-PJ | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
发布紧急采购，3分钟左右您将得到回复。