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参数资料
| 型号： | SSTUB32864EC/G |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32864 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| 封装： | 13.50 X 5.50 MM, 1.05 MM HEIGHT, LEAD FREE, PLASTIC, SOT-536-1, LFBGA-96 |
| 文件页数： | 2/19页 |
| 文件大小： | 113K |
| 代理商： | SSTUB32864EC/G |
SSTUB32864_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 26 March 2007
10 of 19
NXP Semiconductors
SSTUB32864
1.8 V congurable registered buffer for DDR2-800 RDIMM applications
[1]
This parameter is not necessarily production tested.
[2]
Data inputs must be active below a minimum time of tACT(max) after RESET is taken HIGH.
[3]
Data and clock inputs must be held at valid levels (not oating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
[2]
This parameter is not necessarily production tested.
Table 7.
Timing requirements
Recommended operating conditions; Tamb =0 °Cto+70 °C; VDD = 1.8 V ± 0.1 V; unless otherwise specied.
See Figure 6 through Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclock
clock frequency
-
450
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
[1][2] --10
ns
tINACT
differential inputs inactive time
[1][3] --15
ns
tsu
set-up time
DCS before CK
↑, CK ↓,
CSR HIGH
0.6
-
ns
DCS before CK
↑, CK ↓,
CSR LOW
0.5
-
ns
CSR, ODT, CKE, and data
before CK
↑, CK ↓
0.5
-
ns
th
hold time
DCS, CSR, ODT, CKE,
and data after CK
↑, CK ↓
0.4
-
ns
Table 8.
Switching characteristics
Recommended operating conditions; Tamb =0 °Cto+70 °C; VDD = 1.8 V ± 0.1 V;
Class I, Vref =VT =VDD × 0.5 and CL = 10 pF; unless otherwise specied. See Figure 6 through Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fmax
maximum input clock frequency
450
-
MHz
tPDM
peak propagation delay
CK and CK to output
[1] 1.1
-
1.5
ns
tPDMSS
simultaneous switching
peak propagation delay
CK and CK to output
[1][2] -
-
1.6
ns
tPHL
HIGH-to-LOW propagation delay
RESET to output
-
3
ns
Table 9.
Output edge rates
Recommended operating conditions; VDD = 1.8 V ± 0.1 V; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
1
-
4
V/ns
dV/dt_f
falling edge slew rate
1
-
4
V/ns
dV/dt_
absolute difference between dV/dt_r
and dV/dt_f
-
1
V/ns
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相关代理商/技术参数 |
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| SSTUB32865 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications |
| SSTUB32865ET/G,518 | 功能描述:寄存器 1.8V 28B REG RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUB32865ET/G-T | 功能描述:寄存器 1.8V 28B REG BUF/PRTY DDR2-800 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUB32866 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications |
| SSTUB32866_10 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications |
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