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参数资料
型号： SSTUB32868ET/S
厂商： NXP SEMICONDUCTORS
元件分类： 锁存器
英文描述： 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封装： 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件页数： 10/30页
文件大小： 254K
代理商： SSTUB32868ET/S
SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
18 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
[1]
This parameter is not necessarily production tested.
[2]
VREF must be held at a valid input voltage level, and data inputs must be held LOW for a minimum time of tACT(max) after RESET is
taken HIGH.
[3]
VREF, data and clock inputs must be held at valid voltage levels (not floating) a minimum time of tINACT(max) after RESET is taken LOW.
[1]
Includes 350 ps of test-load transmission line delay.
Table 9.
Timing requirements
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk
clock frequency
-
450
MHz
tW
pulse width
CK, CK HIGH or LOW
1
-
ns
tACT
differential inputs active time
[1][2] --10
ns
tINACT
differential inputs inactive
time
[1][3] --15
ns
tsu
set-up time
DCSn before CK
↑, CK↓, CSR HIGH;
CSR before CK
↑, CK↓, DCSn HIGH
0.6
-
ns
DCSn before CK
↑, CK↓, CSR LOW
0.5
-
ns
DODTn, DCKEn ad Dn before CK
↑, CK↓
0.5
-
ns
PAR_IN before CK
↑, CK↓
0.5
-
ns
th
hold time
DCSn, DODTn, DCKEn and Dn after
CK
↑, CK↓
0.4
-
ns
PAR_IN after CK
↑, CK↓
0.4
-
ns
Table 10.
Switching characteristics
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fclk(max)
maximum clock frequency
input
450
-
MHz
tPDM
peak propagation delay
single bit switching;
from CK
↑ and CK↓ to Qn
[1] 1.1
-
1.5
ns
tPLH
LOW to HIGH propagation delay
from CK
↑ and CK↓ to QERR
1.2
-
3
ns
from RESET
↑ to QERR↓
--
3
ns
tPHL
HIGH to LOW propagation delay
from CK
↑ and CK↓ to QERR
1-
2.4
ns
from RESET
↑ to Qn↓
--
3
ns
tPDMSS
simultaneous switching
peak propagation delay
from CK
↑ and CK↓ to Qn
[1] --
1.6
ns
Table 11.
Output edge rates
Over recommended operating conditions, unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
4
V/ns
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
4
V/ns
dV/dt_
Δ
absolute difference between dV/dt_r
and dV/dt_f
(from 20 % to 80 %) or
(from 80 % to 20 %)
--
1
V/ns
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