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参数资料
| 型号： | SSTUB32868ET/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封装： | 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176 |
| 文件页数： | 30/30页 |
| 文件大小： | 254K |
| 代理商： | SSTUB32868ET/S |
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SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
9 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
QODT0A N2
K2
1.8 V
CMOS
outputs
Data outputs that will not be suspended by
the DCS0 and DCS1 control.
QODT0B M7
L7
QODT1A P2
J2
QODT1B M8
L8
Output error
QERR
M3
open-drain
output
Output error bit; generated on clock cycle
after the corresponding data output.
Parity input
PAR_IN
L3
SSTL_18
Parity input. Arrives one clock cycle after
the corresponding data input.
Program inputs
CSGEN
L2L2LVCMOS
input
Chip select gate enable. When HIGH, the
D1 to D28[1] inputs will be latched only
when at least one chip select input is LOW
during the rising edge of the clock. When
LOW, the D1 to D28[1] inputs will be latched
and re-driven on every rising edge of the
clock.
Clock inputs
CK
L1
differential
input
Positive master clock input.
CK
M1
differential
input
Negative master clock input.
Miscellaneous inputs
RESET
M2
LVCMOS
input
Asynchronous reset input. Resets registers
and disables VREF data and clock
differential-input receivers.
VREF
A5, AB5
0.9 V
nominal
Input reference voltage.
VDD
B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6,
H3, H4, H5, H6, K4, K5,
K6, M4, M5, M6, P4, P5,
P6, T3, T4, T5, T6, V3,
V4, V5, V6, Y3, Y4, Y5,
Y6, AB4, AB6
B3, B4, B5, B6, D3, D4,
D5, D6, F3, F4, F5, F6,
H3, H4, H5, H6, K4, K5,
K6, M4, M5, M6, P4, P5,
P6, T3, T4, T5, T6, V3,
V4, V5, V6, Y3, Y4, Y5,
Y6, AB4, AB6
1.8 V
nominal
Power supply voltage.
GND
A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6,
R3, R4, R5, R6, U3, U4,
U5, U6, W3, W4, W5, W6,
AA3, AA4, AA5, AA6
A4, A6, C3, C4, C5, C6,
E3, E4, E5, E6, G3, G4,
G5, G6, J3, J4, J5, J6, L4,
L5, L6, N3, N4, N5, N6,
R3, R4, R5, R6, U3, U4,
U5, U6, W3, W4, W5, W6,
AA3, AA4, AA5, AA6
ground
input
Ground.
SELDR
AB3
LVCMOS
input with
weak
pull-up
Selects output drive strength: ‘HIGH’ for
normal drive; ‘LOW’ for high drive. This pin
will default HIGH if left open-circuit (built-in
weak pull-up resistor).
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
1 : 2 Register A (C = 0)
1 : 2 Register B (C = 1)
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