参数资料
型号: SSTUB32868ET/S
厂商: NXP SEMICONDUCTORS
元件分类: 锁存器
英文描述: 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176
封装: 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176
文件页数: 15/30页
文件大小: 254K
代理商: SSTUB32868ET/S
SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
22 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
11.3 Error output load circuit and voltage measurement
VDD =1.8 V ± 0.1 V.
All input pulses are supplied by generators having the following characteristics:
PRR
≤ 10 MHz; Z
0 =50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
(1) CL includes probe and jig capacitance.
Fig 19. Load circuit, error output measurements
Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect
to RESET input
Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
to clock inputs
CL = 10 pF(1)
VDD
OUT
DUT
test point
RL = 1 kΩ
002aaa500
0.5VDD
tPLH
VDD
0 V
0.15 V
VOH
0 V
output
waveform 2
RESET
002aab903
LVCMOS
VICR
tPHL
0.5VDD
VDD
VOL
timing
inputs
output
waveform 1
Vi(p-p)
VICR
002aab904
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