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参数资料
| 型号： | SSTUB32868ET/S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | 32868 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA176 |
| 封装： | 6 X 15 MM, 0.70 MM PITCH, LEAD FREE, PLASTIC, MO-246, SOT932-1, TFBGA-176 |
| 文件页数： | 4/30页 |
| 文件大小： | 254K |
| 代理商： | SSTUB32868ET/S |
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SSTUB32868_4
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 22 April 2010
12 of 30
NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
during the time from the LOW-to-HIGH transition of RESET until the input receivers are
fully enabled, the design of the SSTUB32868 must ensure that the outputs will remain
LOW, thus ensuring no glitches on the output.
The SSTUB32868 includes a parity checking function. Parity, which arrives one cycle after
the data input to which it applies, is checked on the PAR_IN input of the device. The
corresponding QERR output signal for the data inputs is generated two clock cycles after
the data, to which the QERR signal applies, is registered.
The SSTUB32868 accepts a parity bit from the memory controller on the parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D inputs
(D1 to D5, D7, D9 to D12, D17 to D28 when C = 0; or D1 to D12, D17 to D20, D22, D24 to
D28 when C = 1) and indicates whether a parity error has occurred on the open-drain
QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an
even number of ones across the DIMM-independent data inputs combined with the parity
input bit. To calculate parity, all DIMM-independent D inputs must be tied to a known logic
state.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for a
minimum of two clock cycles or until RESET is driven LOW. If two or more consecutive
parity errors occur, the QERR output is driven LOW and latched LOW for a clock duration
equal to the parity error duration or until RESET is driven LOW. If a parity error occurs on
the clock cycle before the device enters the Low-Power Mode (LPM) and the QERR
output is driven LOW, then it stays latched LOW for the LPM duration plus two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE0, DCKE1,
DODT0, DODT1, DCS0, DCS1, DCS2 and DCS3) are not included in the parity check
computation.
The C input controls the pinout configuration from Register A configuration (when LOW) to
Register B configuration (when HIGH). The C input should not be switched during normal
operation. It should be hard-wired to a valid LOW or HIGH level to configure the register in
the desired mode.
The device also supports low-power active operation by monitoring both system chip
select (DCS0, DCS1, DCS2 and DCS3) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0 and DCS1 inputs are HIGH. If CSGEN or the
DCSn inputs are LOW, the Qn outputs will function normally. Also, if all DCSn inputs are
HIGH, the device will gate the QERR output from changing states. If any of the DCSn are
LOW, the QERR output will function normally. The RESET input has priority over the
DCSn control, and when driven LOW will force the Qn outputs LOW and the QERR output
HIGH. If the chip-select control functionality is not desired, then the CSGEN input can be
hard-wired to ground (GND), in which case the setup time requirement for DCSn would be
the same as for the other D data inputs. To control the Low-power mode with DCSn only,
the CSGEN input should be pulled up to VDD through a pull-up resistor.
The two VREF pins (A5 and AB5) are connected together internally by approximately
150
Ω. However, it is necessary to connect only one of the two VREF pins to the external
Vref power supply. An unused VREF pin should be terminated with a Vref coupling
capacitor.
The SSTUB32868 is available in a TFGBA176 package.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTUB32870AHMLFT | 制造商:Integrated Device Technology Inc 功能描述:DDR2 REGISTER - Tape and Reel |
| SSTUB32871AHLF | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUB32871AHLFT | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:否 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUB32871AHMLF | 功能描述:IC REGIST BUFF 27BIT DDR2 96-BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUB32872AHLF | 功能描述:缓冲器和线路驱动器 RoHS:否 制造商:Micrel 输入线路数量:1 输出线路数量:2 极性:Non-Inverting 电源电压-最大:+/- 5.5 V 电源电压-最小:+/- 2.37 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MSOP-8 封装:Reel |
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