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| 型号： | ST10F168-Q3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件页数： | 37/74页 |
| 文件大小： | 479K |
| 代理商： | ST10F168-Q3 |
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ST10F168
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18 - POWER REDUCTION MODES
Two different power reduction modes with different
levels of power reduction can be entered under
software control.
In Idle mode the CPU is stopped, while the
peripherals continue their operation. Idle mode
can be terminated by any reset or interrupt
request.
In Power Down mode both the CPU and the
peripherals are stopped. Power Down mode can
be configured by software in order to be termi-
nated only by a hardware reset or by an external
interrupt source on fast external interrupt pins.
There are two different operating Power Down
modes:
– Protected power down mode: selected by set-
ting bit PWDCFG in the SYSCON register to ‘0’.
This mode can be used in conjunction with an
external power failure signal which pulls the NMI
pin low when a power failure is imminent. The
microcontroller enters the NMI trap routine and
saves the internal state into RAM. The trap rou-
tine then sets a flag or writes a bit pattern into
specific RAM locations, and executes the
PWRDN instruction. If the NMI pin is still low at
this time, Power Down mode will be entered, if
not program execution continues. During power
down the voltage at the VCC pins can be lowered
to 2.5 V and the contents of the internal RAM will
still be preserved.
– Interruptible
power
down
mode:
this
mode is selected by setting bit PWDCFG in the
SYSCON register. The CPU and peripheral
clocks are frozen, and the oscillator and PLL are
stopped. To exit power down mode with an ex-
ternal interrupt, an EXxIN (x = 7...0) pin has to
be asserted for at least 40ns. This signal ena-
bles the internal oscillator and PLL circuitry, and
turns on the weak pulldown. If the Interrupt was
enabled before entering power down mode, the
device executes the interrupt service routine,
and then resumes execution after the PWRDN
instruction. If the interrupt was disabled, the de-
vice executes the instruction following PWRDN
instruction, and the Interrupt Request Flag re-
mains set until it is cleared by software.
All external bus actions are completed before Idle
or Power Down mode is entered. However, Idle or
Power Down mode is not entered if READY is
enabled, but has not been activated (driven low for
negative polarity, or driven high for positive polar-
ity) during the last bus access.
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