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| 型号： | ST10F168-Q3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 28 X 28 MM, PLASTIC, QFP-144 |
| 文件页数： | 48/74页 |
| 文件大小： | 479K |
| 代理商： | ST10F168-Q3 |
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ST10F168
52/74
Figure 15 : Supply / idle current as a function of operation frequency
20.4 - A/D Converter Characteristics
VDD =5V ±10%, VSS = 0V, 4.0V ≤ VAREF ≤ VDD + 0.1V, VSS - 0.1V ≤ VAGND ≤ VSS + 0.2V, Q6 version :
TA = -40, +85°C and for Q3 version TA = -40°C, +125°C, unless otherwise specified
Notes: 1. VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectively.
2. During the tS sample time the input capacitance Cain can be charged/discharged by the external source. The internal resistance of
the analog source must allow the capacitance to reach its final voltage level within the tS sample time. After the end of the tS sample
time, changes of the analog input voltage have no effect on the conversion result. Values for the tSC sample clock depend on the
programming. Referring to the tC conversion time formula of chapter 13, to the table 17 of page 33 and to the table below:
tS min = 2 tSC min = 2 tCC min = 2 x 24 x TCL = 48 TCL
tS max = 2 tSC max = 2 x 8 tCC max = 2 x 8 x 96 TCL = 1536 TCL
TCL is defined in section 20.5.5 at page 55.
3. The conversion time formula is:
tC =14 tCC +tS + 4 TCL (=14tCC +2 tSC + 4 TCL)
The tC parameter includes the tS sample time, the time for determining the digital result and the time to load the result register with
the result of the conversion. Values for the tCC conversion clock depend on the programming. Referring to the table 17 of page 33 and
to the table below:
tC min = 14 tCC min + tS min + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
tC max = 14 tCC max + tS max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. TUE is tested at VAREF = 5.0V, VAGND = 0V, VCC = 4.9V. It is guaranteed by design characterization for all other voltages within the
defined voltage range. The specified TUE is guaranteed only if an overload condition (see Iov specification) occurs on maximum of 2
not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
During the reset calibration sequence the maximum TUE may be
±4LSB.
Symbol
Parameter
Test
Conditions
Min.
Max.
Unit
VAIN
SR Analog input voltage range
1- 8
VAGND
VAREF
V
tS
CC Sample time
2- 4
48 TCL
1 536 TCL
tC
CC Conversion time
3- 4
388 TCL
2 884 TCL
TUE
CC Total unadjusted error
5
–
± 2
LSB
RAREF SR Internal resistance of reference voltage source
tCC in [ns]
6- 7
–(tCC / 165) - 0.25
k
RASRC SR Internal resistance of analog source
tS in [ns]
2- 7
–(tS / 330) - 0.25
k
CAIN CC ADC input capacitance
7
–33
pF
I[mA]
fCPU [MHz]
5
10
15
20
200
100
10
IIDmax
ICCmax
25
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