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参数资料
| 型号： | ST10R272LT6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, TQFP-100 |
| 文件页数： | 26/77页 |
| 文件大小： | 707K |
| 代理商： | ST10R272LT6 |
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ST10R272L - WATCHDOG TIMER
12
WATCHDOG TIMER
The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the
controller. The Watchdog Timer is always enabled after device reset and can only be disabled
in the time interval until the EINIT (end of initialization) instruction has been executed. In this
way, the chip’s start-up procedure is always monitored. The software must be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to maintain the Watchdog Timer, it will overflow generating an
internal hardware reset and pulling the RSTOUT pin low to reset external hardware
components.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by
128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value
(stored in WDTREL) in order to allow further variation of the monitored time interval. Each
time it is serviced by the application software, the high byte of the Watchdog Timer is
reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock
rounded to 3 significant figures.
011
SSP clock = CPU clock divided by 16
3.13 MBit/s
100
SSP clock = CPU clock divided by 32
1.56 MBit/s
101
SSP clock = CPU clock divided by 64
781 KBit/s
110
SSP clock = CPU clock divided by 128
391 KBit/s
111
SSP clock = CPU clock divided by 256
195 KBit/s
Reload value
in WDTREL
Prescaler for fCPU
2 (WDTIN = ‘0’)
128 (WDTIN = ‘1’)
FFH
10.24 s
655 s
00H
2.62 ms
168 ms
Table 12 Watchdog timer range
SSPCKS Value
Synchronous baud rate
Table 11 Synchronous baud rate and SSPCKS reload values
1
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